pci.c 2.4 KB

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  1. /*
  2. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <pci.h>
  8. #include <pci_rom.h>
  9. #include <asm/pci.h>
  10. #include <asm/arch/qemu.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. void board_pci_setup_hose(struct pci_controller *hose)
  13. {
  14. hose->first_busno = 0;
  15. hose->last_busno = 0;
  16. /* PCI memory space */
  17. pci_set_region(hose->regions + 0,
  18. CONFIG_PCI_MEM_BUS,
  19. CONFIG_PCI_MEM_PHYS,
  20. CONFIG_PCI_MEM_SIZE,
  21. PCI_REGION_MEM);
  22. /* PCI IO space */
  23. pci_set_region(hose->regions + 1,
  24. CONFIG_PCI_IO_BUS,
  25. CONFIG_PCI_IO_PHYS,
  26. CONFIG_PCI_IO_SIZE,
  27. PCI_REGION_IO);
  28. pci_set_region(hose->regions + 2,
  29. CONFIG_PCI_PREF_BUS,
  30. CONFIG_PCI_PREF_PHYS,
  31. CONFIG_PCI_PREF_SIZE,
  32. PCI_REGION_PREFETCH);
  33. pci_set_region(hose->regions + 3,
  34. 0,
  35. 0,
  36. gd->ram_size,
  37. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  38. hose->region_count = 4;
  39. }
  40. int board_pci_post_scan(struct pci_controller *hose)
  41. {
  42. int ret = 0;
  43. ulong start;
  44. pci_dev_t bdf;
  45. struct pci_device_id graphic_card[] = { { 0x1234, 0x1111 } };
  46. u16 device;
  47. int pam, i;
  48. /*
  49. * QEMU emulated graphic card shows in the PCI configuration space with
  50. * PCI vendor id and device id as an artificial pair 0x1234:0x1111.
  51. * It is on PCI bus 0, function 0, but device number is not consistent
  52. * for the two x86 targets it supports. For i440FX and PIIX chipset
  53. * board, it shows as device 2, while for Q35 and ICH9 chipset board,
  54. * it shows as device 1. Here we locate its bdf at run-time based on
  55. * its vendor id and device id pair so we can support both boards.
  56. */
  57. bdf = pci_find_devices(graphic_card, 0);
  58. if (bdf != -1) {
  59. start = get_timer(0);
  60. ret = pci_run_vga_bios(bdf, NULL, PCI_ROM_USE_NATIVE);
  61. debug("BIOS ran in %lums\n", get_timer(start));
  62. }
  63. /*
  64. * i440FX and Q35 chipset have different PAM register offset, but with
  65. * the same bitfield layout. Here we determine the offset based on its
  66. * PCI device ID.
  67. */
  68. device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
  69. pam = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_PAM : Q35_PAM;
  70. /*
  71. * Initialize Programmable Attribute Map (PAM) Registers
  72. *
  73. * Configure legacy segments C/D/E/F to system RAM
  74. */
  75. for (i = 0; i < PAM_NUM; i++)
  76. x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
  77. return ret;
  78. }