tegra114_spi.c 12 KB

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  1. /*
  2. * NVIDIA Tegra SPI controller (T114 and later)
  3. *
  4. * Copyright (c) 2010-2013 NVIDIA Corporation
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This software is licensed under the terms of the GNU General Public
  10. * License version 2, as published by the Free Software Foundation, and
  11. * may be copied, distributed, and modified under those terms.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <dm.h>
  25. #include <asm/io.h>
  26. #include <asm/arch/clock.h>
  27. #include <asm/arch-tegra/clk_rst.h>
  28. #include <spi.h>
  29. #include <fdtdec.h>
  30. #include "tegra_spi.h"
  31. DECLARE_GLOBAL_DATA_PTR;
  32. /* COMMAND1 */
  33. #define SPI_CMD1_GO (1 << 31)
  34. #define SPI_CMD1_M_S (1 << 30)
  35. #define SPI_CMD1_MODE_MASK 0x3
  36. #define SPI_CMD1_MODE_SHIFT 28
  37. #define SPI_CMD1_CS_SEL_MASK 0x3
  38. #define SPI_CMD1_CS_SEL_SHIFT 26
  39. #define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25)
  40. #define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24)
  41. #define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23)
  42. #define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22)
  43. #define SPI_CMD1_CS_SW_HW (1 << 21)
  44. #define SPI_CMD1_CS_SW_VAL (1 << 20)
  45. #define SPI_CMD1_IDLE_SDA_MASK 0x3
  46. #define SPI_CMD1_IDLE_SDA_SHIFT 18
  47. #define SPI_CMD1_BIDIR (1 << 17)
  48. #define SPI_CMD1_LSBI_FE (1 << 16)
  49. #define SPI_CMD1_LSBY_FE (1 << 15)
  50. #define SPI_CMD1_BOTH_EN_BIT (1 << 14)
  51. #define SPI_CMD1_BOTH_EN_BYTE (1 << 13)
  52. #define SPI_CMD1_RX_EN (1 << 12)
  53. #define SPI_CMD1_TX_EN (1 << 11)
  54. #define SPI_CMD1_PACKED (1 << 5)
  55. #define SPI_CMD1_BIT_LEN_MASK 0x1F
  56. #define SPI_CMD1_BIT_LEN_SHIFT 0
  57. /* COMMAND2 */
  58. #define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6)
  59. #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6)
  60. #define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0)
  61. #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0)
  62. /* TRANSFER STATUS */
  63. #define SPI_XFER_STS_RDY (1 << 30)
  64. /* FIFO STATUS */
  65. #define SPI_FIFO_STS_CS_INACTIVE (1 << 31)
  66. #define SPI_FIFO_STS_FRAME_END (1 << 30)
  67. #define SPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15)
  68. #define SPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14)
  69. #define SPI_FIFO_STS_ERR (1 << 8)
  70. #define SPI_FIFO_STS_TX_FIFO_OVF (1 << 7)
  71. #define SPI_FIFO_STS_TX_FIFO_UNR (1 << 6)
  72. #define SPI_FIFO_STS_RX_FIFO_OVF (1 << 5)
  73. #define SPI_FIFO_STS_RX_FIFO_UNR (1 << 4)
  74. #define SPI_FIFO_STS_TX_FIFO_FULL (1 << 3)
  75. #define SPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2)
  76. #define SPI_FIFO_STS_RX_FIFO_FULL (1 << 1)
  77. #define SPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0)
  78. #define SPI_TIMEOUT 1000
  79. #define TEGRA_SPI_MAX_FREQ 52000000
  80. struct spi_regs {
  81. u32 command1; /* 000:SPI_COMMAND1 register */
  82. u32 command2; /* 004:SPI_COMMAND2 register */
  83. u32 timing1; /* 008:SPI_CS_TIM1 register */
  84. u32 timing2; /* 00c:SPI_CS_TIM2 register */
  85. u32 xfer_status;/* 010:SPI_TRANS_STATUS register */
  86. u32 fifo_status;/* 014:SPI_FIFO_STATUS register */
  87. u32 tx_data; /* 018:SPI_TX_DATA register */
  88. u32 rx_data; /* 01c:SPI_RX_DATA register */
  89. u32 dma_ctl; /* 020:SPI_DMA_CTL register */
  90. u32 dma_blk; /* 024:SPI_DMA_BLK register */
  91. u32 rsvd[56]; /* 028-107 reserved */
  92. u32 tx_fifo; /* 108:SPI_FIFO1 register */
  93. u32 rsvd2[31]; /* 10c-187 reserved */
  94. u32 rx_fifo; /* 188:SPI_FIFO2 register */
  95. u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */
  96. };
  97. struct tegra114_spi_priv {
  98. struct spi_regs *regs;
  99. unsigned int freq;
  100. unsigned int mode;
  101. int periph_id;
  102. int valid;
  103. int last_transaction_us;
  104. };
  105. static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
  106. {
  107. struct tegra_spi_platdata *plat = bus->platdata;
  108. const void *blob = gd->fdt_blob;
  109. int node = bus->of_offset;
  110. plat->base = fdtdec_get_addr(blob, node, "reg");
  111. plat->periph_id = clock_decode_periph_id(blob, node);
  112. if (plat->periph_id == PERIPH_ID_NONE) {
  113. debug("%s: could not decode periph id %d\n", __func__,
  114. plat->periph_id);
  115. return -FDT_ERR_NOTFOUND;
  116. }
  117. /* Use 500KHz as a suitable default */
  118. plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
  119. 500000);
  120. plat->deactivate_delay_us = fdtdec_get_int(blob, node,
  121. "spi-deactivate-delay", 0);
  122. debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
  123. __func__, plat->base, plat->periph_id, plat->frequency,
  124. plat->deactivate_delay_us);
  125. return 0;
  126. }
  127. static int tegra114_spi_probe(struct udevice *bus)
  128. {
  129. struct tegra_spi_platdata *plat = dev_get_platdata(bus);
  130. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  131. priv->regs = (struct spi_regs *)plat->base;
  132. priv->last_transaction_us = timer_get_us();
  133. priv->freq = plat->frequency;
  134. priv->periph_id = plat->periph_id;
  135. return 0;
  136. }
  137. static int tegra114_spi_claim_bus(struct udevice *dev)
  138. {
  139. struct udevice *bus = dev->parent;
  140. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  141. struct spi_regs *regs = priv->regs;
  142. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  143. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
  144. /* Clear stale status here */
  145. setbits_le32(&regs->fifo_status,
  146. SPI_FIFO_STS_ERR |
  147. SPI_FIFO_STS_TX_FIFO_OVF |
  148. SPI_FIFO_STS_TX_FIFO_UNR |
  149. SPI_FIFO_STS_RX_FIFO_OVF |
  150. SPI_FIFO_STS_RX_FIFO_UNR |
  151. SPI_FIFO_STS_TX_FIFO_FULL |
  152. SPI_FIFO_STS_TX_FIFO_EMPTY |
  153. SPI_FIFO_STS_RX_FIFO_FULL |
  154. SPI_FIFO_STS_RX_FIFO_EMPTY);
  155. debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
  156. /* Set master mode and sw controlled CS */
  157. setbits_le32(&regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
  158. (priv->mode << SPI_CMD1_MODE_SHIFT));
  159. debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
  160. return 0;
  161. }
  162. /**
  163. * Activate the CS by driving it LOW
  164. *
  165. * @param slave Pointer to spi_slave to which controller has to
  166. * communicate with
  167. */
  168. static void spi_cs_activate(struct udevice *dev)
  169. {
  170. struct udevice *bus = dev->parent;
  171. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  172. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  173. /* If it's too soon to do another transaction, wait */
  174. if (pdata->deactivate_delay_us &&
  175. priv->last_transaction_us) {
  176. ulong delay_us; /* The delay completed so far */
  177. delay_us = timer_get_us() - priv->last_transaction_us;
  178. if (delay_us < pdata->deactivate_delay_us)
  179. udelay(pdata->deactivate_delay_us - delay_us);
  180. }
  181. clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
  182. }
  183. /**
  184. * Deactivate the CS by driving it HIGH
  185. *
  186. * @param slave Pointer to spi_slave to which controller has to
  187. * communicate with
  188. */
  189. static void spi_cs_deactivate(struct udevice *dev)
  190. {
  191. struct udevice *bus = dev->parent;
  192. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  193. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  194. setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
  195. /* Remember time of this transaction so we can honour the bus delay */
  196. if (pdata->deactivate_delay_us)
  197. priv->last_transaction_us = timer_get_us();
  198. debug("Deactivate CS, bus '%s'\n", bus->name);
  199. }
  200. static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
  201. const void *data_out, void *data_in,
  202. unsigned long flags)
  203. {
  204. struct udevice *bus = dev->parent;
  205. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  206. struct spi_regs *regs = priv->regs;
  207. u32 reg, tmpdout, tmpdin = 0;
  208. const u8 *dout = data_out;
  209. u8 *din = data_in;
  210. int num_bytes;
  211. int ret;
  212. debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
  213. __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
  214. if (bitlen % 8)
  215. return -1;
  216. num_bytes = bitlen / 8;
  217. ret = 0;
  218. /* clear all error status bits */
  219. reg = readl(&regs->fifo_status);
  220. writel(reg, &regs->fifo_status);
  221. clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
  222. SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
  223. (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT));
  224. /* set xfer size to 1 block (32 bits) */
  225. writel(0, &regs->dma_blk);
  226. if (flags & SPI_XFER_BEGIN)
  227. spi_cs_activate(dev);
  228. /* handle data in 32-bit chunks */
  229. while (num_bytes > 0) {
  230. int bytes;
  231. int tm, i;
  232. tmpdout = 0;
  233. bytes = (num_bytes > 4) ? 4 : num_bytes;
  234. if (dout != NULL) {
  235. for (i = 0; i < bytes; ++i)
  236. tmpdout = (tmpdout << 8) | dout[i];
  237. dout += bytes;
  238. }
  239. num_bytes -= bytes;
  240. /* clear ready bit */
  241. setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);
  242. clrsetbits_le32(&regs->command1,
  243. SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT,
  244. (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT);
  245. writel(tmpdout, &regs->tx_fifo);
  246. setbits_le32(&regs->command1, SPI_CMD1_GO);
  247. /*
  248. * Wait for SPI transmit FIFO to empty, or to time out.
  249. * The RX FIFO status will be read and cleared last
  250. */
  251. for (tm = 0; tm < SPI_TIMEOUT; ++tm) {
  252. u32 fifo_status, xfer_status;
  253. xfer_status = readl(&regs->xfer_status);
  254. if (!(xfer_status & SPI_XFER_STS_RDY))
  255. continue;
  256. fifo_status = readl(&regs->fifo_status);
  257. if (fifo_status & SPI_FIFO_STS_ERR) {
  258. debug("%s: got a fifo error: ", __func__);
  259. if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF)
  260. debug("tx FIFO overflow ");
  261. if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR)
  262. debug("tx FIFO underrun ");
  263. if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF)
  264. debug("rx FIFO overflow ");
  265. if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR)
  266. debug("rx FIFO underrun ");
  267. if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL)
  268. debug("tx FIFO full ");
  269. if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)
  270. debug("tx FIFO empty ");
  271. if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL)
  272. debug("rx FIFO full ");
  273. if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)
  274. debug("rx FIFO empty ");
  275. debug("\n");
  276. break;
  277. }
  278. if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) {
  279. tmpdin = readl(&regs->rx_fifo);
  280. /* swap bytes read in */
  281. if (din != NULL) {
  282. for (i = bytes - 1; i >= 0; --i) {
  283. din[i] = tmpdin & 0xff;
  284. tmpdin >>= 8;
  285. }
  286. din += bytes;
  287. }
  288. /* We can exit when we've had both RX and TX */
  289. break;
  290. }
  291. }
  292. if (tm >= SPI_TIMEOUT)
  293. ret = tm;
  294. /* clear ACK RDY, etc. bits */
  295. writel(readl(&regs->fifo_status), &regs->fifo_status);
  296. }
  297. if (flags & SPI_XFER_END)
  298. spi_cs_deactivate(dev);
  299. debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
  300. __func__, tmpdin, readl(&regs->fifo_status));
  301. if (ret) {
  302. printf("%s: timeout during SPI transfer, tm %d\n",
  303. __func__, ret);
  304. return -1;
  305. }
  306. return ret;
  307. }
  308. static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
  309. {
  310. struct tegra_spi_platdata *plat = bus->platdata;
  311. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  312. if (speed > plat->frequency)
  313. speed = plat->frequency;
  314. priv->freq = speed;
  315. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  316. return 0;
  317. }
  318. static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
  319. {
  320. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  321. priv->mode = mode;
  322. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  323. return 0;
  324. }
  325. static const struct dm_spi_ops tegra114_spi_ops = {
  326. .claim_bus = tegra114_spi_claim_bus,
  327. .xfer = tegra114_spi_xfer,
  328. .set_speed = tegra114_spi_set_speed,
  329. .set_mode = tegra114_spi_set_mode,
  330. /*
  331. * cs_info is not needed, since we require all chip selects to be
  332. * in the device tree explicitly
  333. */
  334. };
  335. static const struct udevice_id tegra114_spi_ids[] = {
  336. { .compatible = "nvidia,tegra114-spi" },
  337. { }
  338. };
  339. U_BOOT_DRIVER(tegra114_spi) = {
  340. .name = "tegra114_spi",
  341. .id = UCLASS_SPI,
  342. .of_match = tegra114_spi_ids,
  343. .ops = &tegra114_spi_ops,
  344. .ofdata_to_platdata = tegra114_spi_ofdata_to_platdata,
  345. .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
  346. .priv_auto_alloc_size = sizeof(struct tegra114_spi_priv),
  347. .probe = tegra114_spi_probe,
  348. };