sama5_sfr.h 2.0 KB

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  1. /*
  2. * Special Function Register (SFR)
  3. *
  4. * Copyright (C) 2014 Atmel
  5. * Bo Shen <voice.shen@atmel.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #ifndef __SAMA5_SFR_H
  10. #define __SAMA5_SFR_H
  11. struct atmel_sfr {
  12. u32 reserved1; /* 0x00 */
  13. u32 ddrcfg; /* 0x04: DDR Configuration Register */
  14. u32 reserved2; /* 0x08 */
  15. u32 reserved3; /* 0x0c */
  16. u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */
  17. u32 ohciisr; /* 0x14: OHCI Interrupt Status Register */
  18. u32 reserved4[4]; /* 0x18 ~ 0x24 */
  19. u32 secure; /* 0x28: Security Configuration Register */
  20. u32 reserved5[5]; /* 0x2c ~ 0x3c */
  21. u32 ebicfg; /* 0x40: EBI Configuration Register */
  22. u32 reserved6[2]; /* 0x44 ~ 0x48 */
  23. u32 sn0; /* 0x4c */
  24. u32 sn1; /* 0x50 */
  25. u32 aicredir; /* 0x54 */
  26. u32 l2cc_hramc; /* 0x58 */
  27. };
  28. /* Bit field in DDRCFG */
  29. #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000
  30. #define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
  31. /* Bit field in EBICFG */
  32. #define AT91_SFR_EBICFG_DRIVE0 (0x3 << 0)
  33. #define AT91_SFR_EBICFG_DRIVE0_LOW (0x0 << 0)
  34. #define AT91_SFR_EBICFG_DRIVE0_MEDIUM (0x2 << 0)
  35. #define AT91_SFR_EBICFG_DRIVE0_HIGH (0x3 << 0)
  36. #define AT91_SFR_EBICFG_PULL0 (0x3 << 2)
  37. #define AT91_SFR_EBICFG_PULL0_UP (0x0 << 2)
  38. #define AT91_SFR_EBICFG_PULL0_NONE (0x1 << 2)
  39. #define AT91_SFR_EBICFG_PULL0_DOWN (0x3 << 2)
  40. #define AT91_SFR_EBICFG_SCH0 (0x1 << 4)
  41. #define AT91_SFR_EBICFG_SCH0_OFF (0x0 << 4)
  42. #define AT91_SFR_EBICFG_SCH0_ON (0x1 << 4)
  43. #define AT91_SFR_EBICFG_DRIVE1 (0x3 << 8)
  44. #define AT91_SFR_EBICFG_DRIVE1_LOW (0x0 << 8)
  45. #define AT91_SFR_EBICFG_DRIVE1_MEDIUM (0x2 << 8)
  46. #define AT91_SFR_EBICFG_DRIVE1_HIGH (0x3 << 8)
  47. #define AT91_SFR_EBICFG_PULL1 (0x3 << 10)
  48. #define AT91_SFR_EBICFG_PULL1_UP (0x0 << 10)
  49. #define AT91_SFR_EBICFG_PULL1_NONE (0x1 << 10)
  50. #define AT91_SFR_EBICFG_PULL1_DOWN (0x3 << 10)
  51. #define AT91_SFR_EBICFG_SCH1 (0x1 << 12)
  52. #define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12)
  53. #define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12)
  54. /* Bit field in AICREDIR */
  55. #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
  56. #endif