link.dts 4.9 KB

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  1. /dts-v1/;
  2. /include/ "skeleton.dtsi"
  3. /include/ "serial.dtsi"
  4. / {
  5. model = "Google Link";
  6. compatible = "google,link", "intel,celeron-ivybridge";
  7. config {
  8. silent_console = <0>;
  9. };
  10. gpioa {
  11. compatible = "intel,ich6-gpio";
  12. u-boot,dm-pre-reloc;
  13. reg = <0 0x10>;
  14. bank-name = "A";
  15. };
  16. gpiob {
  17. compatible = "intel,ich6-gpio";
  18. u-boot,dm-pre-reloc;
  19. reg = <0x30 0x10>;
  20. bank-name = "B";
  21. };
  22. gpioc {
  23. compatible = "intel,ich6-gpio";
  24. u-boot,dm-pre-reloc;
  25. reg = <0x40 0x10>;
  26. bank-name = "C";
  27. };
  28. chosen {
  29. stdout-path = "/serial";
  30. };
  31. spd {
  32. compatible = "memory-spd";
  33. #address-cells = <1>;
  34. #size-cells = <0>;
  35. elpida_4Gb_1600_x16 {
  36. reg = <0>;
  37. data = [92 10 0b 03 04 19 02 02
  38. 03 52 01 08 0a 00 fe 00
  39. 69 78 69 3c 69 11 18 81
  40. 20 08 3c 3c 01 40 83 81
  41. 00 00 00 00 00 00 00 00
  42. 00 00 00 00 00 00 00 00
  43. 00 00 00 00 00 00 00 00
  44. 00 00 00 00 0f 11 42 00
  45. 00 00 00 00 00 00 00 00
  46. 00 00 00 00 00 00 00 00
  47. 00 00 00 00 00 00 00 00
  48. 00 00 00 00 00 00 00 00
  49. 00 00 00 00 00 00 00 00
  50. 00 00 00 00 00 00 00 00
  51. 00 00 00 00 00 02 fe 00
  52. 11 52 00 00 00 07 7f 37
  53. 45 42 4a 32 30 55 47 36
  54. 45 42 55 30 2d 47 4e 2d
  55. 46 20 30 20 02 fe 00 00
  56. 00 00 00 00 00 00 00 00
  57. 00 00 00 00 00 00 00 00
  58. 00 00 00 00 00 00 00 00
  59. 00 00 00 00 00 00 00 00
  60. 00 00 00 00 00 00 00 00
  61. 00 00 00 00 00 00 00 00
  62. 00 00 00 00 00 00 00 00
  63. 00 00 00 00 00 00 00 00
  64. 00 00 00 00 00 00 00 00
  65. 00 00 00 00 00 00 00 00
  66. 00 00 00 00 00 00 00 00
  67. 00 00 00 00 00 00 00 00
  68. 00 00 00 00 00 00 00 00];
  69. };
  70. samsung_4Gb_1600_1.35v_x16 {
  71. reg = <1>;
  72. data = [92 11 0b 03 04 19 02 02
  73. 03 11 01 08 0a 00 fe 00
  74. 69 78 69 3c 69 11 18 81
  75. f0 0a 3c 3c 01 40 83 01
  76. 00 80 00 00 00 00 00 00
  77. 00 00 00 00 00 00 00 00
  78. 00 00 00 00 00 00 00 00
  79. 00 00 00 00 0f 11 02 00
  80. 00 00 00 00 00 00 00 00
  81. 00 00 00 00 00 00 00 00
  82. 00 00 00 00 00 00 00 00
  83. 00 00 00 00 00 00 00 00
  84. 00 00 00 00 00 00 00 00
  85. 00 00 00 00 00 00 00 00
  86. 00 00 00 00 00 80 ce 01
  87. 00 00 00 00 00 00 6a 04
  88. 4d 34 37 31 42 35 36 37
  89. 34 42 48 30 2d 59 4b 30
  90. 20 20 00 00 80 ce 00 00
  91. 00 00 00 00 00 00 00 00
  92. 00 00 00 00 00 00 00 00
  93. 00 00 00 00 00 00 00 00
  94. 00 00 00 00 00 00 00 00
  95. 00 00 00 00 00 00 00 00
  96. 00 00 00 00 00 00 00 00
  97. 00 00 00 00 00 00 00 00
  98. 00 00 00 00 00 00 00 00
  99. 00 00 00 00 00 00 00 00
  100. 00 00 00 00 00 00 00 00
  101. 00 00 00 00 00 00 00 00
  102. 00 00 00 00 00 00 00 00
  103. 00 00 00 00 00 00 00 00];
  104. };
  105. micron_4Gb_1600_1.35v_x16 {
  106. reg = <2>;
  107. data = [92 11 0b 03 04 19 02 02
  108. 03 11 01 08 0a 00 fe 00
  109. 69 78 69 3c 69 11 18 81
  110. 20 08 3c 3c 01 40 83 05
  111. 00 00 00 00 00 00 00 00
  112. 00 00 00 00 00 00 00 00
  113. 00 00 00 00 00 00 00 00
  114. 00 00 00 00 0f 01 02 00
  115. 00 00 00 00 00 00 00 00
  116. 00 00 00 00 00 00 00 00
  117. 00 00 00 00 00 00 00 00
  118. 00 00 00 00 00 00 00 00
  119. 00 00 00 00 00 00 00 00
  120. 00 00 00 00 00 00 00 00
  121. 00 00 00 00 00 80 2c 00
  122. 00 00 00 00 00 00 ad 75
  123. 34 4b 54 46 32 35 36 36
  124. 34 48 5a 2d 31 47 36 45
  125. 31 20 45 31 80 2c 00 00
  126. 00 00 00 00 00 00 00 00
  127. 00 00 00 00 00 00 00 00
  128. 00 00 00 00 00 00 00 00
  129. ff ff ff ff ff ff ff ff
  130. ff ff ff ff ff ff ff ff
  131. ff ff ff ff ff ff ff ff
  132. ff ff ff ff ff ff ff ff
  133. ff ff ff ff ff ff ff ff
  134. ff ff ff ff ff ff ff ff
  135. ff ff ff ff ff ff ff ff
  136. ff ff ff ff ff ff ff ff
  137. ff ff ff ff ff ff ff ff
  138. ff ff ff ff ff ff ff ff];
  139. };
  140. };
  141. spi {
  142. #address-cells = <1>;
  143. #size-cells = <0>;
  144. compatible = "intel,ich9";
  145. spi-flash@0 {
  146. reg = <0>;
  147. compatible = "winbond,w25q64", "spi-flash";
  148. memory-map = <0xff800000 0x00800000>;
  149. };
  150. };
  151. pci {
  152. sata {
  153. compatible = "intel,pantherpoint-ahci";
  154. intel,sata-mode = "ahci";
  155. intel,sata-port-map = <1>;
  156. intel,sata-port0-gen3-tx = <0x00880a7f>;
  157. };
  158. gma {
  159. compatible = "intel,gma";
  160. intel,dp_hotplug = <0 0 0x06>;
  161. intel,panel-port-select = <1>;
  162. intel,panel-power-cycle-delay = <6>;
  163. intel,panel-power-up-delay = <2000>;
  164. intel,panel-power-down-delay = <500>;
  165. intel,panel-power-backlight-on-delay = <2000>;
  166. intel,panel-power-backlight-off-delay = <2000>;
  167. intel,cpu-backlight = <0x00000200>;
  168. intel,pch-backlight = <0x04000000>;
  169. };
  170. lpc {
  171. compatible = "intel,lpc";
  172. #address-cells = <1>;
  173. #size-cells = <1>;
  174. gen-dec = <0x800 0xfc 0x900 0xfc>;
  175. intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
  176. intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
  177. 0x80 0x80 0x80 0x80>;
  178. intel,gpi-routing = <0 0 0 0 0 0 0 2
  179. 1 0 0 0 0 0 0 0>;
  180. /* Enable EC SMI source */
  181. intel,alt-gp-smi-enable = <0x0100>;
  182. cros-ec@200 {
  183. compatible = "google,cros-ec";
  184. reg = <0x204 1 0x200 1 0x880 0x80>;
  185. /* Describes the flash memory within the EC */
  186. #address-cells = <1>;
  187. #size-cells = <1>;
  188. flash@8000000 {
  189. reg = <0x08000000 0x20000>;
  190. erase-value = <0xff>;
  191. };
  192. };
  193. };
  194. };
  195. microcode {
  196. update@0 {
  197. #include "microcode/m12306a9_0000001b.dtsi"
  198. };
  199. };
  200. };