spi_flash.c 26 KB

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  1. /*
  2. * SPI Flash Core
  3. *
  4. * Copyright (C) 2015 Jagan Teki <jteki@openedev.com>
  5. * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
  6. * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
  7. * Copyright (C) 2008 Atmel Corporation
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #include <common.h>
  12. #include <errno.h>
  13. #include <malloc.h>
  14. #include <mapmem.h>
  15. #include <spi.h>
  16. #include <spi_flash.h>
  17. #include <linux/log2.h>
  18. #include "sf_internal.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. static void spi_flash_addr(u32 addr, u8 *cmd)
  21. {
  22. /* cmd[0] is actual command */
  23. cmd[1] = addr >> 16;
  24. cmd[2] = addr >> 8;
  25. cmd[3] = addr >> 0;
  26. }
  27. static int read_sr(struct spi_flash *flash, u8 *rs)
  28. {
  29. int ret;
  30. u8 cmd;
  31. cmd = CMD_READ_STATUS;
  32. ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
  33. if (ret < 0) {
  34. debug("SF: fail to read status register\n");
  35. return ret;
  36. }
  37. return 0;
  38. }
  39. static int read_fsr(struct spi_flash *flash, u8 *fsr)
  40. {
  41. int ret;
  42. const u8 cmd = CMD_FLAG_STATUS;
  43. ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1);
  44. if (ret < 0) {
  45. debug("SF: fail to read flag status register\n");
  46. return ret;
  47. }
  48. return 0;
  49. }
  50. static int write_sr(struct spi_flash *flash, u8 ws)
  51. {
  52. u8 cmd;
  53. int ret;
  54. cmd = CMD_WRITE_STATUS;
  55. ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1);
  56. if (ret < 0) {
  57. debug("SF: fail to write status register\n");
  58. return ret;
  59. }
  60. return 0;
  61. }
  62. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  63. static int read_cr(struct spi_flash *flash, u8 *rc)
  64. {
  65. int ret;
  66. u8 cmd;
  67. cmd = CMD_READ_CONFIG;
  68. ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
  69. if (ret < 0) {
  70. debug("SF: fail to read config register\n");
  71. return ret;
  72. }
  73. return 0;
  74. }
  75. static int write_cr(struct spi_flash *flash, u8 wc)
  76. {
  77. u8 data[2];
  78. u8 cmd;
  79. int ret;
  80. ret = read_sr(flash, &data[0]);
  81. if (ret < 0)
  82. return ret;
  83. cmd = CMD_WRITE_STATUS;
  84. data[1] = wc;
  85. ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
  86. if (ret) {
  87. debug("SF: fail to write config register\n");
  88. return ret;
  89. }
  90. return 0;
  91. }
  92. #endif
  93. #ifdef CONFIG_SPI_FLASH_STMICRO
  94. static int read_evcr(struct spi_flash *flash, u8 *evcr)
  95. {
  96. int ret;
  97. const u8 cmd = CMD_READ_EVCR;
  98. ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1);
  99. if (ret < 0) {
  100. debug("SF: error reading EVCR\n");
  101. return ret;
  102. }
  103. return 0;
  104. }
  105. static int write_evcr(struct spi_flash *flash, u8 evcr)
  106. {
  107. u8 cmd;
  108. int ret;
  109. cmd = CMD_WRITE_EVCR;
  110. ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1);
  111. if (ret < 0) {
  112. debug("SF: error while writing EVCR register\n");
  113. return ret;
  114. }
  115. return 0;
  116. }
  117. #endif
  118. #ifdef CONFIG_SPI_FLASH_BAR
  119. static int spi_flash_write_bar(struct spi_flash *flash, u32 offset)
  120. {
  121. u8 cmd, bank_sel;
  122. int ret;
  123. bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
  124. if (bank_sel == flash->bank_curr)
  125. goto bar_end;
  126. cmd = flash->bank_write_cmd;
  127. ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
  128. if (ret < 0) {
  129. debug("SF: fail to write bank register\n");
  130. return ret;
  131. }
  132. bar_end:
  133. flash->bank_curr = bank_sel;
  134. return flash->bank_curr;
  135. }
  136. static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0)
  137. {
  138. u8 curr_bank = 0;
  139. int ret;
  140. if (flash->size <= SPI_FLASH_16MB_BOUN)
  141. goto bar_end;
  142. switch (idcode0) {
  143. case SPI_FLASH_CFI_MFR_SPANSION:
  144. flash->bank_read_cmd = CMD_BANKADDR_BRRD;
  145. flash->bank_write_cmd = CMD_BANKADDR_BRWR;
  146. break;
  147. default:
  148. flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
  149. flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
  150. }
  151. ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
  152. &curr_bank, 1);
  153. if (ret) {
  154. debug("SF: fail to read bank addr register\n");
  155. return ret;
  156. }
  157. bar_end:
  158. flash->bank_curr = curr_bank;
  159. return 0;
  160. }
  161. #endif
  162. #ifdef CONFIG_SF_DUAL_FLASH
  163. static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
  164. {
  165. struct spi_slave *spi = flash->spi;
  166. switch (flash->dual_flash) {
  167. case SF_DUAL_STACKED_FLASH:
  168. if (*addr >= (flash->size >> 1)) {
  169. *addr -= flash->size >> 1;
  170. spi->flags |= SPI_XFER_U_PAGE;
  171. } else {
  172. spi->flags &= ~SPI_XFER_U_PAGE;
  173. }
  174. break;
  175. case SF_DUAL_PARALLEL_FLASH:
  176. *addr >>= flash->shift;
  177. break;
  178. default:
  179. debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash);
  180. break;
  181. }
  182. }
  183. #endif
  184. static int spi_flash_sr_ready(struct spi_flash *flash)
  185. {
  186. u8 sr;
  187. int ret;
  188. ret = read_sr(flash, &sr);
  189. if (ret < 0)
  190. return ret;
  191. return !(sr & STATUS_WIP);
  192. }
  193. static int spi_flash_fsr_ready(struct spi_flash *flash)
  194. {
  195. u8 fsr;
  196. int ret;
  197. ret = read_fsr(flash, &fsr);
  198. if (ret < 0)
  199. return ret;
  200. return fsr & STATUS_PEC;
  201. }
  202. static int spi_flash_ready(struct spi_flash *flash)
  203. {
  204. int sr, fsr;
  205. sr = spi_flash_sr_ready(flash);
  206. if (sr < 0)
  207. return sr;
  208. fsr = 1;
  209. if (flash->flags & SNOR_F_USE_FSR) {
  210. fsr = spi_flash_fsr_ready(flash);
  211. if (fsr < 0)
  212. return fsr;
  213. }
  214. return sr && fsr;
  215. }
  216. static int spi_flash_cmd_wait_ready(struct spi_flash *flash,
  217. unsigned long timeout)
  218. {
  219. int timebase, ret;
  220. timebase = get_timer(0);
  221. while (get_timer(timebase) < timeout) {
  222. ret = spi_flash_ready(flash);
  223. if (ret < 0)
  224. return ret;
  225. if (ret)
  226. return 0;
  227. }
  228. printf("SF: Timeout!\n");
  229. return -ETIMEDOUT;
  230. }
  231. int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
  232. size_t cmd_len, const void *buf, size_t buf_len)
  233. {
  234. struct spi_slave *spi = flash->spi;
  235. unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
  236. int ret;
  237. if (buf == NULL)
  238. timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
  239. ret = spi_claim_bus(spi);
  240. if (ret) {
  241. debug("SF: unable to claim SPI bus\n");
  242. return ret;
  243. }
  244. ret = spi_flash_cmd_write_enable(flash);
  245. if (ret < 0) {
  246. debug("SF: enabling write failed\n");
  247. return ret;
  248. }
  249. ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
  250. if (ret < 0) {
  251. debug("SF: write cmd failed\n");
  252. return ret;
  253. }
  254. ret = spi_flash_cmd_wait_ready(flash, timeout);
  255. if (ret < 0) {
  256. debug("SF: write %s timed out\n",
  257. timeout == SPI_FLASH_PROG_TIMEOUT ?
  258. "program" : "page erase");
  259. return ret;
  260. }
  261. spi_release_bus(spi);
  262. return ret;
  263. }
  264. int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
  265. {
  266. u32 erase_size, erase_addr;
  267. u8 cmd[SPI_FLASH_CMD_LEN];
  268. int ret = -1;
  269. erase_size = flash->erase_size;
  270. if (offset % erase_size || len % erase_size) {
  271. debug("SF: Erase offset/length not multiple of erase size\n");
  272. return -1;
  273. }
  274. if (flash->flash_is_locked) {
  275. if (flash->flash_is_locked(flash, offset, len) > 0) {
  276. printf("offset 0x%x is protected and cannot be erased\n",
  277. offset);
  278. return -EINVAL;
  279. }
  280. }
  281. cmd[0] = flash->erase_cmd;
  282. while (len) {
  283. erase_addr = offset;
  284. #ifdef CONFIG_SF_DUAL_FLASH
  285. if (flash->dual_flash > SF_SINGLE_FLASH)
  286. spi_flash_dual(flash, &erase_addr);
  287. #endif
  288. #ifdef CONFIG_SPI_FLASH_BAR
  289. ret = spi_flash_write_bar(flash, erase_addr);
  290. if (ret < 0)
  291. return ret;
  292. #endif
  293. spi_flash_addr(erase_addr, cmd);
  294. debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
  295. cmd[2], cmd[3], erase_addr);
  296. ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
  297. if (ret < 0) {
  298. debug("SF: erase failed\n");
  299. break;
  300. }
  301. offset += erase_size;
  302. len -= erase_size;
  303. }
  304. return ret;
  305. }
  306. int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
  307. size_t len, const void *buf)
  308. {
  309. struct spi_slave *spi = flash->spi;
  310. unsigned long byte_addr, page_size;
  311. u32 write_addr;
  312. size_t chunk_len, actual;
  313. u8 cmd[SPI_FLASH_CMD_LEN];
  314. int ret = -1;
  315. page_size = flash->page_size;
  316. if (flash->flash_is_locked) {
  317. if (flash->flash_is_locked(flash, offset, len) > 0) {
  318. printf("offset 0x%x is protected and cannot be written\n",
  319. offset);
  320. return -EINVAL;
  321. }
  322. }
  323. cmd[0] = flash->write_cmd;
  324. for (actual = 0; actual < len; actual += chunk_len) {
  325. write_addr = offset;
  326. #ifdef CONFIG_SF_DUAL_FLASH
  327. if (flash->dual_flash > SF_SINGLE_FLASH)
  328. spi_flash_dual(flash, &write_addr);
  329. #endif
  330. #ifdef CONFIG_SPI_FLASH_BAR
  331. ret = spi_flash_write_bar(flash, write_addr);
  332. if (ret < 0)
  333. return ret;
  334. #endif
  335. byte_addr = offset % page_size;
  336. chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
  337. if (spi->max_write_size)
  338. chunk_len = min(chunk_len,
  339. (size_t)spi->max_write_size);
  340. spi_flash_addr(write_addr, cmd);
  341. debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
  342. buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
  343. ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
  344. buf + actual, chunk_len);
  345. if (ret < 0) {
  346. debug("SF: write failed\n");
  347. break;
  348. }
  349. offset += chunk_len;
  350. }
  351. return ret;
  352. }
  353. int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
  354. size_t cmd_len, void *data, size_t data_len)
  355. {
  356. struct spi_slave *spi = flash->spi;
  357. int ret;
  358. ret = spi_claim_bus(spi);
  359. if (ret) {
  360. debug("SF: unable to claim SPI bus\n");
  361. return ret;
  362. }
  363. ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
  364. if (ret < 0) {
  365. debug("SF: read cmd failed\n");
  366. return ret;
  367. }
  368. spi_release_bus(spi);
  369. return ret;
  370. }
  371. void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len)
  372. {
  373. memcpy(data, offset, len);
  374. }
  375. int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
  376. size_t len, void *data)
  377. {
  378. struct spi_slave *spi = flash->spi;
  379. u8 *cmd, cmdsz;
  380. u32 remain_len, read_len, read_addr;
  381. int bank_sel = 0;
  382. int ret = -1;
  383. /* Handle memory-mapped SPI */
  384. if (flash->memory_map) {
  385. ret = spi_claim_bus(spi);
  386. if (ret) {
  387. debug("SF: unable to claim SPI bus\n");
  388. return ret;
  389. }
  390. spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP);
  391. spi_flash_copy_mmap(data, flash->memory_map + offset, len);
  392. spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
  393. spi_release_bus(spi);
  394. return 0;
  395. }
  396. cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
  397. cmd = calloc(1, cmdsz);
  398. if (!cmd) {
  399. debug("SF: Failed to allocate cmd\n");
  400. return -ENOMEM;
  401. }
  402. cmd[0] = flash->read_cmd;
  403. while (len) {
  404. read_addr = offset;
  405. #ifdef CONFIG_SF_DUAL_FLASH
  406. if (flash->dual_flash > SF_SINGLE_FLASH)
  407. spi_flash_dual(flash, &read_addr);
  408. #endif
  409. #ifdef CONFIG_SPI_FLASH_BAR
  410. ret = spi_flash_write_bar(flash, read_addr);
  411. if (ret < 0)
  412. return ret;
  413. bank_sel = flash->bank_curr;
  414. #endif
  415. remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
  416. (bank_sel + 1)) - offset;
  417. if (len < remain_len)
  418. read_len = len;
  419. else
  420. read_len = remain_len;
  421. spi_flash_addr(read_addr, cmd);
  422. ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
  423. if (ret < 0) {
  424. debug("SF: read failed\n");
  425. break;
  426. }
  427. offset += read_len;
  428. len -= read_len;
  429. data += read_len;
  430. }
  431. free(cmd);
  432. return ret;
  433. }
  434. #ifdef CONFIG_SPI_FLASH_SST
  435. static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
  436. {
  437. struct spi_slave *spi = flash->spi;
  438. int ret;
  439. u8 cmd[4] = {
  440. CMD_SST_BP,
  441. offset >> 16,
  442. offset >> 8,
  443. offset,
  444. };
  445. debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
  446. spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset);
  447. ret = spi_flash_cmd_write_enable(flash);
  448. if (ret)
  449. return ret;
  450. ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1);
  451. if (ret)
  452. return ret;
  453. return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
  454. }
  455. int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
  456. const void *buf)
  457. {
  458. struct spi_slave *spi = flash->spi;
  459. size_t actual, cmd_len;
  460. int ret;
  461. u8 cmd[4];
  462. ret = spi_claim_bus(spi);
  463. if (ret) {
  464. debug("SF: Unable to claim SPI bus\n");
  465. return ret;
  466. }
  467. /* If the data is not word aligned, write out leading single byte */
  468. actual = offset % 2;
  469. if (actual) {
  470. ret = sst_byte_write(flash, offset, buf);
  471. if (ret)
  472. goto done;
  473. }
  474. offset += actual;
  475. ret = spi_flash_cmd_write_enable(flash);
  476. if (ret)
  477. goto done;
  478. cmd_len = 4;
  479. cmd[0] = CMD_SST_AAI_WP;
  480. cmd[1] = offset >> 16;
  481. cmd[2] = offset >> 8;
  482. cmd[3] = offset;
  483. for (; actual < len - 1; actual += 2) {
  484. debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
  485. spi_w8r8(spi, CMD_READ_STATUS), buf + actual,
  486. cmd[0], offset);
  487. ret = spi_flash_cmd_write(spi, cmd, cmd_len,
  488. buf + actual, 2);
  489. if (ret) {
  490. debug("SF: sst word program failed\n");
  491. break;
  492. }
  493. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
  494. if (ret)
  495. break;
  496. cmd_len = 1;
  497. offset += 2;
  498. }
  499. if (!ret)
  500. ret = spi_flash_cmd_write_disable(flash);
  501. /* If there is a single trailing byte, write it out */
  502. if (!ret && actual != len)
  503. ret = sst_byte_write(flash, offset, buf + actual);
  504. done:
  505. debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
  506. ret ? "failure" : "success", len, offset - actual);
  507. spi_release_bus(spi);
  508. return ret;
  509. }
  510. int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
  511. const void *buf)
  512. {
  513. struct spi_slave *spi = flash->spi;
  514. size_t actual;
  515. int ret;
  516. ret = spi_claim_bus(spi);
  517. if (ret) {
  518. debug("SF: Unable to claim SPI bus\n");
  519. return ret;
  520. }
  521. for (actual = 0; actual < len; actual++) {
  522. ret = sst_byte_write(flash, offset, buf + actual);
  523. if (ret) {
  524. debug("SF: sst byte program failed\n");
  525. break;
  526. }
  527. offset++;
  528. }
  529. if (!ret)
  530. ret = spi_flash_cmd_write_disable(flash);
  531. debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
  532. ret ? "failure" : "success", len, offset - actual);
  533. spi_release_bus(spi);
  534. return ret;
  535. }
  536. #endif
  537. #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
  538. static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
  539. u32 *len)
  540. {
  541. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  542. int shift = ffs(mask) - 1;
  543. int pow;
  544. if (!(sr & mask)) {
  545. /* No protection */
  546. *ofs = 0;
  547. *len = 0;
  548. } else {
  549. pow = ((sr & mask) ^ mask) >> shift;
  550. *len = flash->size >> pow;
  551. *ofs = flash->size - *len;
  552. }
  553. }
  554. /*
  555. * Return 1 if the entire region is locked, 0 otherwise
  556. */
  557. static int stm_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len,
  558. u8 sr)
  559. {
  560. loff_t lock_offs;
  561. u32 lock_len;
  562. stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
  563. return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
  564. }
  565. /*
  566. * Check if a region of the flash is (completely) locked. See stm_lock() for
  567. * more info.
  568. *
  569. * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
  570. * negative on errors.
  571. */
  572. int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
  573. {
  574. int status;
  575. u8 sr;
  576. status = read_sr(flash, &sr);
  577. if (status < 0)
  578. return status;
  579. return stm_is_locked_sr(flash, ofs, len, sr);
  580. }
  581. /*
  582. * Lock a region of the flash. Compatible with ST Micro and similar flash.
  583. * Supports only the block protection bits BP{0,1,2} in the status register
  584. * (SR). Does not support these features found in newer SR bitfields:
  585. * - TB: top/bottom protect - only handle TB=0 (top protect)
  586. * - SEC: sector/block protect - only handle SEC=0 (block protect)
  587. * - CMP: complement protect - only support CMP=0 (range is not complemented)
  588. *
  589. * Sample table portion for 8MB flash (Winbond w25q64fw):
  590. *
  591. * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
  592. * --------------------------------------------------------------------------
  593. * X | X | 0 | 0 | 0 | NONE | NONE
  594. * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
  595. * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
  596. * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
  597. * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
  598. * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
  599. * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
  600. * X | X | 1 | 1 | 1 | 8 MB | ALL
  601. *
  602. * Returns negative on errors, 0 on success.
  603. */
  604. int stm_lock(struct spi_flash *flash, u32 ofs, size_t len)
  605. {
  606. u8 status_old, status_new;
  607. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  608. u8 shift = ffs(mask) - 1, pow, val;
  609. int ret;
  610. ret = read_sr(flash, &status_old);
  611. if (ret < 0)
  612. return ret;
  613. /* SPI NOR always locks to the end */
  614. if (ofs + len != flash->size) {
  615. /* Does combined region extend to end? */
  616. if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len,
  617. status_old))
  618. return -EINVAL;
  619. len = flash->size - ofs;
  620. }
  621. /*
  622. * Need smallest pow such that:
  623. *
  624. * 1 / (2^pow) <= (len / size)
  625. *
  626. * so (assuming power-of-2 size) we do:
  627. *
  628. * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
  629. */
  630. pow = ilog2(flash->size) - ilog2(len);
  631. val = mask - (pow << shift);
  632. if (val & ~mask)
  633. return -EINVAL;
  634. /* Don't "lock" with no region! */
  635. if (!(val & mask))
  636. return -EINVAL;
  637. status_new = (status_old & ~mask) | val;
  638. /* Only modify protection if it will not unlock other areas */
  639. if ((status_new & mask) <= (status_old & mask))
  640. return -EINVAL;
  641. write_sr(flash, status_new);
  642. return 0;
  643. }
  644. /*
  645. * Unlock a region of the flash. See stm_lock() for more info
  646. *
  647. * Returns negative on errors, 0 on success.
  648. */
  649. int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
  650. {
  651. uint8_t status_old, status_new;
  652. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  653. u8 shift = ffs(mask) - 1, pow, val;
  654. int ret;
  655. ret = read_sr(flash, &status_old);
  656. if (ret < 0)
  657. return ret;
  658. /* Cannot unlock; would unlock larger region than requested */
  659. if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size,
  660. status_old))
  661. return -EINVAL;
  662. /*
  663. * Need largest pow such that:
  664. *
  665. * 1 / (2^pow) >= (len / size)
  666. *
  667. * so (assuming power-of-2 size) we do:
  668. *
  669. * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
  670. */
  671. pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len));
  672. if (ofs + len == flash->size) {
  673. val = 0; /* fully unlocked */
  674. } else {
  675. val = mask - (pow << shift);
  676. /* Some power-of-two sizes are not supported */
  677. if (val & ~mask)
  678. return -EINVAL;
  679. }
  680. status_new = (status_old & ~mask) | val;
  681. /* Only modify protection if it will not lock other areas */
  682. if ((status_new & mask) >= (status_old & mask))
  683. return -EINVAL;
  684. write_sr(flash, status_new);
  685. return 0;
  686. }
  687. #endif
  688. #ifdef CONFIG_SPI_FLASH_MACRONIX
  689. static int macronix_quad_enable(struct spi_flash *flash)
  690. {
  691. u8 qeb_status;
  692. int ret;
  693. ret = read_sr(flash, &qeb_status);
  694. if (ret < 0)
  695. return ret;
  696. if (qeb_status & STATUS_QEB_MXIC) {
  697. debug("SF: mxic: QEB is already set\n");
  698. } else {
  699. ret = write_sr(flash, STATUS_QEB_MXIC);
  700. if (ret < 0)
  701. return ret;
  702. }
  703. return ret;
  704. }
  705. #endif
  706. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  707. static int spansion_quad_enable(struct spi_flash *flash)
  708. {
  709. u8 qeb_status;
  710. int ret;
  711. ret = read_cr(flash, &qeb_status);
  712. if (ret < 0)
  713. return ret;
  714. if (qeb_status & STATUS_QEB_WINSPAN) {
  715. debug("SF: winspan: QEB is already set\n");
  716. } else {
  717. ret = write_cr(flash, STATUS_QEB_WINSPAN);
  718. if (ret < 0)
  719. return ret;
  720. }
  721. return ret;
  722. }
  723. #endif
  724. #ifdef CONFIG_SPI_FLASH_STMICRO
  725. static int micron_quad_enable(struct spi_flash *flash)
  726. {
  727. u8 qeb_status;
  728. int ret;
  729. ret = read_evcr(flash, &qeb_status);
  730. if (ret < 0)
  731. return ret;
  732. if (!(qeb_status & STATUS_QEB_MICRON))
  733. return 0;
  734. ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON);
  735. if (ret < 0)
  736. return ret;
  737. /* read EVCR and check it */
  738. ret = read_evcr(flash, &qeb_status);
  739. if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) {
  740. printf("SF: Micron EVCR Quad bit not clear\n");
  741. return -EINVAL;
  742. }
  743. return ret;
  744. }
  745. #endif
  746. static int set_quad_mode(struct spi_flash *flash, u8 idcode0)
  747. {
  748. switch (idcode0) {
  749. #ifdef CONFIG_SPI_FLASH_MACRONIX
  750. case SPI_FLASH_CFI_MFR_MACRONIX:
  751. return macronix_quad_enable(flash);
  752. #endif
  753. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  754. case SPI_FLASH_CFI_MFR_SPANSION:
  755. case SPI_FLASH_CFI_MFR_WINBOND:
  756. return spansion_quad_enable(flash);
  757. #endif
  758. #ifdef CONFIG_SPI_FLASH_STMICRO
  759. case SPI_FLASH_CFI_MFR_STMICRO:
  760. return micron_quad_enable(flash);
  761. #endif
  762. default:
  763. printf("SF: Need set QEB func for %02x flash\n", idcode0);
  764. return -1;
  765. }
  766. }
  767. #if CONFIG_IS_ENABLED(OF_CONTROL)
  768. int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
  769. {
  770. fdt_addr_t addr;
  771. fdt_size_t size;
  772. int node;
  773. /* If there is no node, do nothing */
  774. node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
  775. if (node < 0)
  776. return 0;
  777. addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
  778. if (addr == FDT_ADDR_T_NONE) {
  779. debug("%s: Cannot decode address\n", __func__);
  780. return 0;
  781. }
  782. if (flash->size != size) {
  783. debug("%s: Memory map must cover entire device\n", __func__);
  784. return -1;
  785. }
  786. flash->memory_map = map_sysmem(addr, size);
  787. return 0;
  788. }
  789. #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
  790. int spi_flash_scan(struct spi_flash *flash)
  791. {
  792. struct spi_slave *spi = flash->spi;
  793. const struct spi_flash_params *params;
  794. u16 jedec, ext_jedec;
  795. u8 cmd, idcode[5];
  796. int ret;
  797. static u8 spi_read_cmds_array[] = {
  798. CMD_READ_ARRAY_SLOW,
  799. CMD_READ_ARRAY_FAST,
  800. CMD_READ_DUAL_OUTPUT_FAST,
  801. CMD_READ_DUAL_IO_FAST,
  802. CMD_READ_QUAD_OUTPUT_FAST,
  803. CMD_READ_QUAD_IO_FAST };
  804. /* Read the ID codes */
  805. ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
  806. if (ret) {
  807. printf("SF: Failed to get idcodes\n");
  808. return -EINVAL;
  809. }
  810. #ifdef DEBUG
  811. printf("SF: Got idcodes\n");
  812. print_buffer(0, idcode, 1, sizeof(idcode), 0);
  813. #endif
  814. jedec = idcode[1] << 8 | idcode[2];
  815. ext_jedec = idcode[3] << 8 | idcode[4];
  816. /* Validate params from spi_flash_params table */
  817. params = spi_flash_params_table;
  818. for (; params->name != NULL; params++) {
  819. if ((params->jedec >> 16) == idcode[0]) {
  820. if ((params->jedec & 0xFFFF) == jedec) {
  821. if (params->ext_jedec == 0)
  822. break;
  823. else if (params->ext_jedec == ext_jedec)
  824. break;
  825. }
  826. }
  827. }
  828. if (!params->name) {
  829. printf("SF: Unsupported flash IDs: ");
  830. printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
  831. idcode[0], jedec, ext_jedec);
  832. return -EPROTONOSUPPORT;
  833. }
  834. /* Flash powers up read-only, so clear BP# bits */
  835. if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL ||
  836. idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX ||
  837. idcode[0] == SPI_FLASH_CFI_MFR_SST)
  838. write_sr(flash, 0);
  839. /* Assign spi data */
  840. flash->name = params->name;
  841. flash->memory_map = spi->memory_map;
  842. flash->dual_flash = spi->option;
  843. /* Assign spi flash flags */
  844. if (params->flags & SST_WR)
  845. flash->flags |= SNOR_F_SST_WR;
  846. /* Assign spi_flash ops */
  847. #ifndef CONFIG_DM_SPI_FLASH
  848. flash->write = spi_flash_cmd_write_ops;
  849. #if defined(CONFIG_SPI_FLASH_SST)
  850. if (flash->flags & SNOR_F_SST_WR) {
  851. if (spi->mode & SPI_TX_BYTE)
  852. flash->write = sst_write_bp;
  853. else
  854. flash->write = sst_write_wp;
  855. }
  856. #endif
  857. flash->erase = spi_flash_cmd_erase_ops;
  858. flash->read = spi_flash_cmd_read_ops;
  859. #endif
  860. /* lock hooks are flash specific - assign them based on idcode0 */
  861. switch (idcode[0]) {
  862. #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
  863. case SPI_FLASH_CFI_MFR_STMICRO:
  864. case SPI_FLASH_CFI_MFR_SST:
  865. flash->flash_lock = stm_lock;
  866. flash->flash_unlock = stm_unlock;
  867. flash->flash_is_locked = stm_is_locked;
  868. #endif
  869. break;
  870. default:
  871. debug("SF: Lock ops not supported for %02x flash\n", idcode[0]);
  872. }
  873. /* Compute the flash size */
  874. flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
  875. /*
  876. * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the
  877. * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with
  878. * the 0x4d00 Extended JEDEC code have 512b pages. All of the others
  879. * have 256b pages.
  880. */
  881. if (ext_jedec == 0x4d00) {
  882. if ((jedec == 0x0215) || (jedec == 0x216))
  883. flash->page_size = 256;
  884. else
  885. flash->page_size = 512;
  886. } else {
  887. flash->page_size = 256;
  888. }
  889. flash->page_size <<= flash->shift;
  890. flash->sector_size = params->sector_size << flash->shift;
  891. flash->size = flash->sector_size * params->nr_sectors << flash->shift;
  892. #ifdef CONFIG_SF_DUAL_FLASH
  893. if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
  894. flash->size <<= 1;
  895. #endif
  896. /* Compute erase sector and command */
  897. if (params->flags & SECT_4K) {
  898. flash->erase_cmd = CMD_ERASE_4K;
  899. flash->erase_size = 4096 << flash->shift;
  900. } else if (params->flags & SECT_32K) {
  901. flash->erase_cmd = CMD_ERASE_32K;
  902. flash->erase_size = 32768 << flash->shift;
  903. } else {
  904. flash->erase_cmd = CMD_ERASE_64K;
  905. flash->erase_size = flash->sector_size;
  906. }
  907. /* Now erase size becomes valid sector size */
  908. flash->sector_size = flash->erase_size;
  909. /* Look for the fastest read cmd */
  910. cmd = fls(params->e_rd_cmd & spi->op_mode_rx);
  911. if (cmd) {
  912. cmd = spi_read_cmds_array[cmd - 1];
  913. flash->read_cmd = cmd;
  914. } else {
  915. /* Go for default supported read cmd */
  916. flash->read_cmd = CMD_READ_ARRAY_FAST;
  917. }
  918. /* Not require to look for fastest only two write cmds yet */
  919. if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
  920. flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
  921. else
  922. /* Go for default supported write cmd */
  923. flash->write_cmd = CMD_PAGE_PROGRAM;
  924. /* Set the quad enable bit - only for quad commands */
  925. if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
  926. (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
  927. (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
  928. ret = set_quad_mode(flash, idcode[0]);
  929. if (ret) {
  930. debug("SF: Fail to set QEB for %02x\n", idcode[0]);
  931. return -EINVAL;
  932. }
  933. }
  934. /* Read dummy_byte: dummy byte is determined based on the
  935. * dummy cycles of a particular command.
  936. * Fast commands - dummy_byte = dummy_cycles/8
  937. * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
  938. * For I/O commands except cmd[0] everything goes on no.of lines
  939. * based on particular command but incase of fast commands except
  940. * data all go on single line irrespective of command.
  941. */
  942. switch (flash->read_cmd) {
  943. case CMD_READ_QUAD_IO_FAST:
  944. flash->dummy_byte = 2;
  945. break;
  946. case CMD_READ_ARRAY_SLOW:
  947. flash->dummy_byte = 0;
  948. break;
  949. default:
  950. flash->dummy_byte = 1;
  951. }
  952. #ifdef CONFIG_SPI_FLASH_STMICRO
  953. if (params->flags & E_FSR)
  954. flash->flags |= SNOR_F_USE_FSR;
  955. #endif
  956. /* Configure the BAR - discover bank cmds and read current bank */
  957. #ifdef CONFIG_SPI_FLASH_BAR
  958. ret = spi_flash_read_bar(flash, idcode[0]);
  959. if (ret < 0)
  960. return ret;
  961. #endif
  962. #if CONFIG_IS_ENABLED(OF_CONTROL)
  963. ret = spi_flash_decode_fdt(gd->fdt_blob, flash);
  964. if (ret) {
  965. debug("SF: FDT decode error\n");
  966. return -EINVAL;
  967. }
  968. #endif
  969. #ifndef CONFIG_SPL_BUILD
  970. printf("SF: Detected %s with page size ", flash->name);
  971. print_size(flash->page_size, ", erase size ");
  972. print_size(flash->erase_size, ", total ");
  973. print_size(flash->size, "");
  974. if (flash->memory_map)
  975. printf(", mapped at %p", flash->memory_map);
  976. puts("\n");
  977. #endif
  978. #ifndef CONFIG_SPI_FLASH_BAR
  979. if (((flash->dual_flash == SF_SINGLE_FLASH) &&
  980. (flash->size > SPI_FLASH_16MB_BOUN)) ||
  981. ((flash->dual_flash > SF_SINGLE_FLASH) &&
  982. (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
  983. puts("SF: Warning - Only lower 16MiB accessible,");
  984. puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
  985. }
  986. #endif
  987. return ret;
  988. }