xilinx.c 6.9 KB

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  1. /*
  2. * (C) Copyright 2012-2013, Xilinx, Michal Simek
  3. *
  4. * (C) Copyright 2002
  5. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  6. * Keith Outwater, keith_outwater@mvis.com
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. /*
  11. * Xilinx FPGA support
  12. */
  13. #include <common.h>
  14. #include <fpga.h>
  15. #include <virtex2.h>
  16. #include <spartan2.h>
  17. #include <spartan3.h>
  18. #include <zynqpl.h>
  19. /* Local Static Functions */
  20. static int xilinx_validate(xilinx_desc *desc, char *fn);
  21. /* ------------------------------------------------------------------------- */
  22. int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
  23. bitstream_type bstype)
  24. {
  25. unsigned int length;
  26. unsigned int swapsize;
  27. unsigned char *dataptr;
  28. unsigned int i;
  29. const fpga_desc *desc;
  30. xilinx_desc *xdesc;
  31. dataptr = (unsigned char *)fpgadata;
  32. /* Find out fpga_description */
  33. desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
  34. /* Assign xilinx device description */
  35. xdesc = desc->devdesc;
  36. /* skip the first bytes of the bitsteam, their meaning is unknown */
  37. length = (*dataptr << 8) + *(dataptr + 1);
  38. dataptr += 2;
  39. dataptr += length;
  40. /* get design name (identifier, length, string) */
  41. length = (*dataptr << 8) + *(dataptr + 1);
  42. dataptr += 2;
  43. if (*dataptr++ != 0x61) {
  44. debug("%s: Design name id not recognized in bitstream\n",
  45. __func__);
  46. return FPGA_FAIL;
  47. }
  48. length = (*dataptr << 8) + *(dataptr + 1);
  49. dataptr += 2;
  50. printf(" design filename = \"%s\"\n", dataptr);
  51. dataptr += length;
  52. /* get part number (identifier, length, string) */
  53. if (*dataptr++ != 0x62) {
  54. printf("%s: Part number id not recognized in bitstream\n",
  55. __func__);
  56. return FPGA_FAIL;
  57. }
  58. length = (*dataptr << 8) + *(dataptr + 1);
  59. dataptr += 2;
  60. if (xdesc->name) {
  61. i = (ulong)strstr((char *)dataptr, xdesc->name);
  62. if (!i) {
  63. printf("%s: Wrong bitstream ID for this device\n",
  64. __func__);
  65. printf("%s: Bitstream ID %s, current device ID %d/%s\n",
  66. __func__, dataptr, devnum, xdesc->name);
  67. return FPGA_FAIL;
  68. }
  69. } else {
  70. printf("%s: Please fill correct device ID to xilinx_desc\n",
  71. __func__);
  72. }
  73. printf(" part number = \"%s\"\n", dataptr);
  74. dataptr += length;
  75. /* get date (identifier, length, string) */
  76. if (*dataptr++ != 0x63) {
  77. printf("%s: Date identifier not recognized in bitstream\n",
  78. __func__);
  79. return FPGA_FAIL;
  80. }
  81. length = (*dataptr << 8) + *(dataptr+1);
  82. dataptr += 2;
  83. printf(" date = \"%s\"\n", dataptr);
  84. dataptr += length;
  85. /* get time (identifier, length, string) */
  86. if (*dataptr++ != 0x64) {
  87. printf("%s: Time identifier not recognized in bitstream\n",
  88. __func__);
  89. return FPGA_FAIL;
  90. }
  91. length = (*dataptr << 8) + *(dataptr+1);
  92. dataptr += 2;
  93. printf(" time = \"%s\"\n", dataptr);
  94. dataptr += length;
  95. /* get fpga data length (identifier, length) */
  96. if (*dataptr++ != 0x65) {
  97. printf("%s: Data length id not recognized in bitstream\n",
  98. __func__);
  99. return FPGA_FAIL;
  100. }
  101. swapsize = ((unsigned int) *dataptr << 24) +
  102. ((unsigned int) *(dataptr + 1) << 16) +
  103. ((unsigned int) *(dataptr + 2) << 8) +
  104. ((unsigned int) *(dataptr + 3));
  105. dataptr += 4;
  106. printf(" bytes in bitstream = %d\n", swapsize);
  107. return fpga_load(devnum, dataptr, swapsize, bstype);
  108. }
  109. int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
  110. bitstream_type bstype)
  111. {
  112. if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
  113. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  114. return FPGA_FAIL;
  115. }
  116. if (!desc->operations || !desc->operations->load) {
  117. printf("%s: Missing load operation\n", __func__);
  118. return FPGA_FAIL;
  119. }
  120. return desc->operations->load(desc, buf, bsize, bstype);
  121. }
  122. #if defined(CONFIG_CMD_FPGA_LOADFS)
  123. int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
  124. fpga_fs_info *fpga_fsinfo)
  125. {
  126. if (!xilinx_validate(desc, (char *)__func__)) {
  127. printf("%s: Invalid device descriptor\n", __func__);
  128. return FPGA_FAIL;
  129. }
  130. if (!desc->operations || !desc->operations->loadfs) {
  131. printf("%s: Missing loadfs operation\n", __func__);
  132. return FPGA_FAIL;
  133. }
  134. return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
  135. }
  136. #endif
  137. int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  138. {
  139. if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
  140. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  141. return FPGA_FAIL;
  142. }
  143. if (!desc->operations || !desc->operations->dump) {
  144. printf("%s: Missing dump operation\n", __func__);
  145. return FPGA_FAIL;
  146. }
  147. return desc->operations->dump(desc, buf, bsize);
  148. }
  149. int xilinx_info(xilinx_desc *desc)
  150. {
  151. int ret_val = FPGA_FAIL;
  152. if (xilinx_validate (desc, (char *)__FUNCTION__)) {
  153. printf ("Family: \t");
  154. switch (desc->family) {
  155. case xilinx_spartan2:
  156. printf ("Spartan-II\n");
  157. break;
  158. case xilinx_spartan3:
  159. printf ("Spartan-III\n");
  160. break;
  161. case xilinx_virtex2:
  162. printf ("Virtex-II\n");
  163. break;
  164. case xilinx_zynq:
  165. printf("Zynq PL\n");
  166. break;
  167. case xilinx_zynqmp:
  168. printf("ZynqMP PL\n");
  169. break;
  170. /* Add new family types here */
  171. default:
  172. printf ("Unknown family type, %d\n", desc->family);
  173. }
  174. printf ("Interface type:\t");
  175. switch (desc->iface) {
  176. case slave_serial:
  177. printf ("Slave Serial\n");
  178. break;
  179. case master_serial: /* Not used */
  180. printf ("Master Serial\n");
  181. break;
  182. case slave_parallel:
  183. printf ("Slave Parallel\n");
  184. break;
  185. case jtag_mode: /* Not used */
  186. printf ("JTAG Mode\n");
  187. break;
  188. case slave_selectmap:
  189. printf ("Slave SelectMap Mode\n");
  190. break;
  191. case master_selectmap:
  192. printf ("Master SelectMap Mode\n");
  193. break;
  194. case devcfg:
  195. printf("Device configuration interface (Zynq)\n");
  196. break;
  197. case csu_dma:
  198. printf("csu_dma configuration interface (ZynqMP)\n");
  199. break;
  200. /* Add new interface types here */
  201. default:
  202. printf ("Unsupported interface type, %d\n", desc->iface);
  203. }
  204. printf("Device Size: \t%zd bytes\n"
  205. "Cookie: \t0x%x (%d)\n",
  206. desc->size, desc->cookie, desc->cookie);
  207. if (desc->name)
  208. printf("Device name: \t%s\n", desc->name);
  209. if (desc->iface_fns)
  210. printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
  211. else
  212. printf ("No Device Function Table.\n");
  213. if (desc->operations && desc->operations->info)
  214. desc->operations->info(desc);
  215. ret_val = FPGA_SUCCESS;
  216. } else {
  217. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  218. }
  219. return ret_val;
  220. }
  221. /* ------------------------------------------------------------------------- */
  222. static int xilinx_validate(xilinx_desc *desc, char *fn)
  223. {
  224. int ret_val = false;
  225. if (desc) {
  226. if ((desc->family > min_xilinx_type) &&
  227. (desc->family < max_xilinx_type)) {
  228. if ((desc->iface > min_xilinx_iface_type) &&
  229. (desc->iface < max_xilinx_iface_type)) {
  230. if (desc->size) {
  231. ret_val = true;
  232. } else
  233. printf ("%s: NULL part size\n", fn);
  234. } else
  235. printf ("%s: Invalid Interface type, %d\n",
  236. fn, desc->iface);
  237. } else
  238. printf ("%s: Invalid family type, %d\n", fn, desc->family);
  239. } else
  240. printf ("%s: NULL descriptor!\n", fn);
  241. return ret_val;
  242. }