start.S 2.9 KB

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  1. /*
  2. * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <asm-offsets.h>
  7. #include <config.h>
  8. #include <linux/linkage.h>
  9. #include <asm/arcregs.h>
  10. ENTRY(_start)
  11. ; ARCompact devices are not supposed to be SMP so master/slave check
  12. ; makes no sense.
  13. #ifdef CONFIG_ISA_ARCV2
  14. ; Non-masters will be halted immediately, they might be kicked later
  15. ; by platform code right before passing control to the Linux kernel
  16. ; in bootm.c:boot_jump_linux().
  17. lr r5, [identity]
  18. lsr r5, r5, 8
  19. bmsk r5, r5, 7
  20. cmp r5, 0
  21. mov.nz r0, r5
  22. bz .Lmaster_proceed
  23. flag 1
  24. nop
  25. nop
  26. nop
  27. .Lmaster_proceed:
  28. #endif
  29. /* Setup interrupt vector base that matches "__text_start" */
  30. sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
  31. ; Disable/enable I-cache according to configuration
  32. lr r5, [ARC_BCR_IC_BUILD]
  33. breq r5, 0, 1f ; I$ doesn't exist
  34. lr r5, [ARC_AUX_IC_CTRL]
  35. #ifndef CONFIG_SYS_ICACHE_OFF
  36. bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
  37. #else
  38. bset r5, r5, 0 ; I$ exists, but is not used
  39. #endif
  40. sr r5, [ARC_AUX_IC_CTRL]
  41. mov r5, 1
  42. sr r5, [ARC_AUX_IC_IVIC]
  43. ; As per ARC HS databook (see chapter 5.3.3.2)
  44. ; it is required to add 3 NOPs after each write to IC_IVIC.
  45. nop
  46. nop
  47. nop
  48. 1:
  49. ; Disable/enable D-cache according to configuration
  50. lr r5, [ARC_BCR_DC_BUILD]
  51. breq r5, 0, 1f ; D$ doesn't exist
  52. lr r5, [ARC_AUX_DC_CTRL]
  53. bclr r5, r5, 6 ; Invalidate (discard w/o wback)
  54. #ifndef CONFIG_SYS_DCACHE_OFF
  55. bclr r5, r5, 0 ; Enable (+Inv)
  56. #else
  57. bset r5, r5, 0 ; Disable (+Inv)
  58. #endif
  59. sr r5, [ARC_AUX_DC_CTRL]
  60. mov r5, 1
  61. sr r5, [ARC_AUX_DC_IVDC]
  62. 1:
  63. #ifdef CONFIG_ISA_ARCV2
  64. ; Disable System-Level Cache (SLC)
  65. lr r5, [ARC_BCR_SLC]
  66. breq r5, 0, 1f ; SLC doesn't exist
  67. lr r5, [ARC_AUX_SLC_CTRL]
  68. bclr r5, r5, 6 ; Invalidate (discard w/o wback)
  69. bclr r5, r5, 0 ; Enable (+Inv)
  70. sr r5, [ARC_AUX_SLC_CTRL]
  71. 1:
  72. #endif
  73. /* Establish C runtime stack and frame */
  74. mov %sp, CONFIG_SYS_INIT_SP_ADDR
  75. mov %fp, %sp
  76. /* Allocate reserved area from current top of stack */
  77. mov %r0, %sp
  78. bl board_init_f_alloc_reserve
  79. /* Set stack below reserved area, adjust frame pointer accordingly */
  80. mov %sp, %r0
  81. mov %fp, %sp
  82. /* Initialize reserved area - note: r0 already contains address */
  83. bl board_init_f_init_reserve
  84. /* Zero the one and only argument of "board_init_f" */
  85. mov_s %r0, 0
  86. j board_init_f
  87. ENDPROC(_start)
  88. /*
  89. * void board_init_f_r_trampoline(stack-pointer address)
  90. *
  91. * This "function" does not return, instead it continues in RAM
  92. * after relocating the monitor code.
  93. *
  94. * r0 = new stack-pointer
  95. */
  96. ENTRY(board_init_f_r_trampoline)
  97. /* Set up the stack- and frame-pointers */
  98. mov %sp, %r0
  99. mov %fp, %sp
  100. /* Update position of intterupt vector table */
  101. lr %r0, [ARC_AUX_INTR_VEC_BASE]
  102. ld %r1, [%r25, GD_RELOC_OFF]
  103. add %r0, %r0, %r1
  104. sr %r0, [ARC_AUX_INTR_VEC_BASE]
  105. /* Re-enter U-Boot by calling board_init_f_r */
  106. j board_init_f_r
  107. ENDPROC(board_init_f_r_trampoline)