mmc.c 37 KB

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  1. /*
  2. * Copyright 2008, Freescale Semiconductor, Inc
  3. * Andy Fleming
  4. *
  5. * Based vaguely on the Linux code
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <command.h>
  12. #include <dm.h>
  13. #include <dm/device-internal.h>
  14. #include <errno.h>
  15. #include <mmc.h>
  16. #include <part.h>
  17. #include <malloc.h>
  18. #include <memalign.h>
  19. #include <linux/list.h>
  20. #include <div64.h>
  21. #include "mmc_private.h"
  22. __weak int board_mmc_getwp(struct mmc *mmc)
  23. {
  24. return -1;
  25. }
  26. int mmc_getwp(struct mmc *mmc)
  27. {
  28. int wp;
  29. wp = board_mmc_getwp(mmc);
  30. if (wp < 0) {
  31. if (mmc->cfg->ops->getwp)
  32. wp = mmc->cfg->ops->getwp(mmc);
  33. else
  34. wp = 0;
  35. }
  36. return wp;
  37. }
  38. __weak int board_mmc_getcd(struct mmc *mmc)
  39. {
  40. return -1;
  41. }
  42. int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  43. {
  44. int ret;
  45. #ifdef CONFIG_MMC_TRACE
  46. int i;
  47. u8 *ptr;
  48. printf("CMD_SEND:%d\n", cmd->cmdidx);
  49. printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
  50. ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
  51. if (ret) {
  52. printf("\t\tRET\t\t\t %d\n", ret);
  53. } else {
  54. switch (cmd->resp_type) {
  55. case MMC_RSP_NONE:
  56. printf("\t\tMMC_RSP_NONE\n");
  57. break;
  58. case MMC_RSP_R1:
  59. printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
  60. cmd->response[0]);
  61. break;
  62. case MMC_RSP_R1b:
  63. printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
  64. cmd->response[0]);
  65. break;
  66. case MMC_RSP_R2:
  67. printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
  68. cmd->response[0]);
  69. printf("\t\t \t\t 0x%08X \n",
  70. cmd->response[1]);
  71. printf("\t\t \t\t 0x%08X \n",
  72. cmd->response[2]);
  73. printf("\t\t \t\t 0x%08X \n",
  74. cmd->response[3]);
  75. printf("\n");
  76. printf("\t\t\t\t\tDUMPING DATA\n");
  77. for (i = 0; i < 4; i++) {
  78. int j;
  79. printf("\t\t\t\t\t%03d - ", i*4);
  80. ptr = (u8 *)&cmd->response[i];
  81. ptr += 3;
  82. for (j = 0; j < 4; j++)
  83. printf("%02X ", *ptr--);
  84. printf("\n");
  85. }
  86. break;
  87. case MMC_RSP_R3:
  88. printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
  89. cmd->response[0]);
  90. break;
  91. default:
  92. printf("\t\tERROR MMC rsp not supported\n");
  93. break;
  94. }
  95. }
  96. #else
  97. ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
  98. #endif
  99. return ret;
  100. }
  101. int mmc_send_status(struct mmc *mmc, int timeout)
  102. {
  103. struct mmc_cmd cmd;
  104. int err, retries = 5;
  105. #ifdef CONFIG_MMC_TRACE
  106. int status;
  107. #endif
  108. cmd.cmdidx = MMC_CMD_SEND_STATUS;
  109. cmd.resp_type = MMC_RSP_R1;
  110. if (!mmc_host_is_spi(mmc))
  111. cmd.cmdarg = mmc->rca << 16;
  112. while (1) {
  113. err = mmc_send_cmd(mmc, &cmd, NULL);
  114. if (!err) {
  115. if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
  116. (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
  117. MMC_STATE_PRG)
  118. break;
  119. else if (cmd.response[0] & MMC_STATUS_MASK) {
  120. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  121. printf("Status Error: 0x%08X\n",
  122. cmd.response[0]);
  123. #endif
  124. return COMM_ERR;
  125. }
  126. } else if (--retries < 0)
  127. return err;
  128. if (timeout-- <= 0)
  129. break;
  130. udelay(1000);
  131. }
  132. #ifdef CONFIG_MMC_TRACE
  133. status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
  134. printf("CURR STATE:%d\n", status);
  135. #endif
  136. if (timeout <= 0) {
  137. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  138. printf("Timeout waiting card ready\n");
  139. #endif
  140. return TIMEOUT;
  141. }
  142. return 0;
  143. }
  144. int mmc_set_blocklen(struct mmc *mmc, int len)
  145. {
  146. struct mmc_cmd cmd;
  147. if (mmc->ddr_mode)
  148. return 0;
  149. cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
  150. cmd.resp_type = MMC_RSP_R1;
  151. cmd.cmdarg = len;
  152. return mmc_send_cmd(mmc, &cmd, NULL);
  153. }
  154. static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
  155. lbaint_t blkcnt)
  156. {
  157. struct mmc_cmd cmd;
  158. struct mmc_data data;
  159. if (blkcnt > 1)
  160. cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
  161. else
  162. cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
  163. if (mmc->high_capacity)
  164. cmd.cmdarg = start;
  165. else
  166. cmd.cmdarg = start * mmc->read_bl_len;
  167. cmd.resp_type = MMC_RSP_R1;
  168. data.dest = dst;
  169. data.blocks = blkcnt;
  170. data.blocksize = mmc->read_bl_len;
  171. data.flags = MMC_DATA_READ;
  172. if (mmc_send_cmd(mmc, &cmd, &data))
  173. return 0;
  174. if (blkcnt > 1) {
  175. cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  176. cmd.cmdarg = 0;
  177. cmd.resp_type = MMC_RSP_R1b;
  178. if (mmc_send_cmd(mmc, &cmd, NULL)) {
  179. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  180. printf("mmc fail to send stop cmd\n");
  181. #endif
  182. return 0;
  183. }
  184. }
  185. return blkcnt;
  186. }
  187. #ifdef CONFIG_BLK
  188. ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
  189. #else
  190. ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
  191. void *dst)
  192. #endif
  193. {
  194. #ifdef CONFIG_BLK
  195. struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
  196. #endif
  197. int dev_num = block_dev->devnum;
  198. int err;
  199. lbaint_t cur, blocks_todo = blkcnt;
  200. if (blkcnt == 0)
  201. return 0;
  202. struct mmc *mmc = find_mmc_device(dev_num);
  203. if (!mmc)
  204. return 0;
  205. err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
  206. if (err < 0)
  207. return 0;
  208. if ((start + blkcnt) > block_dev->lba) {
  209. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  210. printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
  211. start + blkcnt, block_dev->lba);
  212. #endif
  213. return 0;
  214. }
  215. if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
  216. debug("%s: Failed to set blocklen\n", __func__);
  217. return 0;
  218. }
  219. do {
  220. cur = (blocks_todo > mmc->cfg->b_max) ?
  221. mmc->cfg->b_max : blocks_todo;
  222. if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
  223. debug("%s: Failed to read blocks\n", __func__);
  224. return 0;
  225. }
  226. blocks_todo -= cur;
  227. start += cur;
  228. dst += cur * mmc->read_bl_len;
  229. } while (blocks_todo > 0);
  230. return blkcnt;
  231. }
  232. static int mmc_go_idle(struct mmc *mmc)
  233. {
  234. struct mmc_cmd cmd;
  235. int err;
  236. udelay(1000);
  237. cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
  238. cmd.cmdarg = 0;
  239. cmd.resp_type = MMC_RSP_NONE;
  240. err = mmc_send_cmd(mmc, &cmd, NULL);
  241. if (err)
  242. return err;
  243. udelay(2000);
  244. return 0;
  245. }
  246. static int sd_send_op_cond(struct mmc *mmc)
  247. {
  248. int timeout = 1000;
  249. int err;
  250. struct mmc_cmd cmd;
  251. while (1) {
  252. cmd.cmdidx = MMC_CMD_APP_CMD;
  253. cmd.resp_type = MMC_RSP_R1;
  254. cmd.cmdarg = 0;
  255. err = mmc_send_cmd(mmc, &cmd, NULL);
  256. if (err)
  257. return err;
  258. cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
  259. cmd.resp_type = MMC_RSP_R3;
  260. /*
  261. * Most cards do not answer if some reserved bits
  262. * in the ocr are set. However, Some controller
  263. * can set bit 7 (reserved for low voltages), but
  264. * how to manage low voltages SD card is not yet
  265. * specified.
  266. */
  267. cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
  268. (mmc->cfg->voltages & 0xff8000);
  269. if (mmc->version == SD_VERSION_2)
  270. cmd.cmdarg |= OCR_HCS;
  271. err = mmc_send_cmd(mmc, &cmd, NULL);
  272. if (err)
  273. return err;
  274. if (cmd.response[0] & OCR_BUSY)
  275. break;
  276. if (timeout-- <= 0)
  277. return UNUSABLE_ERR;
  278. udelay(1000);
  279. }
  280. if (mmc->version != SD_VERSION_2)
  281. mmc->version = SD_VERSION_1_0;
  282. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  283. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  284. cmd.resp_type = MMC_RSP_R3;
  285. cmd.cmdarg = 0;
  286. err = mmc_send_cmd(mmc, &cmd, NULL);
  287. if (err)
  288. return err;
  289. }
  290. mmc->ocr = cmd.response[0];
  291. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  292. mmc->rca = 0;
  293. return 0;
  294. }
  295. static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
  296. {
  297. struct mmc_cmd cmd;
  298. int err;
  299. cmd.cmdidx = MMC_CMD_SEND_OP_COND;
  300. cmd.resp_type = MMC_RSP_R3;
  301. cmd.cmdarg = 0;
  302. if (use_arg && !mmc_host_is_spi(mmc))
  303. cmd.cmdarg = OCR_HCS |
  304. (mmc->cfg->voltages &
  305. (mmc->ocr & OCR_VOLTAGE_MASK)) |
  306. (mmc->ocr & OCR_ACCESS_MODE);
  307. err = mmc_send_cmd(mmc, &cmd, NULL);
  308. if (err)
  309. return err;
  310. mmc->ocr = cmd.response[0];
  311. return 0;
  312. }
  313. static int mmc_send_op_cond(struct mmc *mmc)
  314. {
  315. int err, i;
  316. /* Some cards seem to need this */
  317. mmc_go_idle(mmc);
  318. /* Asking to the card its capabilities */
  319. for (i = 0; i < 2; i++) {
  320. err = mmc_send_op_cond_iter(mmc, i != 0);
  321. if (err)
  322. return err;
  323. /* exit if not busy (flag seems to be inverted) */
  324. if (mmc->ocr & OCR_BUSY)
  325. break;
  326. }
  327. mmc->op_cond_pending = 1;
  328. return 0;
  329. }
  330. static int mmc_complete_op_cond(struct mmc *mmc)
  331. {
  332. struct mmc_cmd cmd;
  333. int timeout = 1000;
  334. uint start;
  335. int err;
  336. mmc->op_cond_pending = 0;
  337. if (!(mmc->ocr & OCR_BUSY)) {
  338. start = get_timer(0);
  339. while (1) {
  340. err = mmc_send_op_cond_iter(mmc, 1);
  341. if (err)
  342. return err;
  343. if (mmc->ocr & OCR_BUSY)
  344. break;
  345. if (get_timer(start) > timeout)
  346. return UNUSABLE_ERR;
  347. udelay(100);
  348. }
  349. }
  350. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  351. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  352. cmd.resp_type = MMC_RSP_R3;
  353. cmd.cmdarg = 0;
  354. err = mmc_send_cmd(mmc, &cmd, NULL);
  355. if (err)
  356. return err;
  357. mmc->ocr = cmd.response[0];
  358. }
  359. mmc->version = MMC_VERSION_UNKNOWN;
  360. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  361. mmc->rca = 1;
  362. return 0;
  363. }
  364. static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
  365. {
  366. struct mmc_cmd cmd;
  367. struct mmc_data data;
  368. int err;
  369. /* Get the Card Status Register */
  370. cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
  371. cmd.resp_type = MMC_RSP_R1;
  372. cmd.cmdarg = 0;
  373. data.dest = (char *)ext_csd;
  374. data.blocks = 1;
  375. data.blocksize = MMC_MAX_BLOCK_LEN;
  376. data.flags = MMC_DATA_READ;
  377. err = mmc_send_cmd(mmc, &cmd, &data);
  378. return err;
  379. }
  380. int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
  381. {
  382. struct mmc_cmd cmd;
  383. int timeout = 1000;
  384. int ret;
  385. cmd.cmdidx = MMC_CMD_SWITCH;
  386. cmd.resp_type = MMC_RSP_R1b;
  387. cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
  388. (index << 16) |
  389. (value << 8);
  390. ret = mmc_send_cmd(mmc, &cmd, NULL);
  391. /* Waiting for the ready status */
  392. if (!ret)
  393. ret = mmc_send_status(mmc, timeout);
  394. return ret;
  395. }
  396. static int mmc_change_freq(struct mmc *mmc)
  397. {
  398. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  399. char cardtype;
  400. int err;
  401. mmc->card_caps = 0;
  402. if (mmc_host_is_spi(mmc))
  403. return 0;
  404. /* Only version 4 supports high-speed */
  405. if (mmc->version < MMC_VERSION_4)
  406. return 0;
  407. mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
  408. err = mmc_send_ext_csd(mmc, ext_csd);
  409. if (err)
  410. return err;
  411. cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
  412. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
  413. if (err)
  414. return err;
  415. /* Now check to see that it worked */
  416. err = mmc_send_ext_csd(mmc, ext_csd);
  417. if (err)
  418. return err;
  419. /* No high-speed support */
  420. if (!ext_csd[EXT_CSD_HS_TIMING])
  421. return 0;
  422. /* High Speed is set, there are two types: 52MHz and 26MHz */
  423. if (cardtype & EXT_CSD_CARD_TYPE_52) {
  424. if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
  425. mmc->card_caps |= MMC_MODE_DDR_52MHz;
  426. mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  427. } else {
  428. mmc->card_caps |= MMC_MODE_HS;
  429. }
  430. return 0;
  431. }
  432. static int mmc_set_capacity(struct mmc *mmc, int part_num)
  433. {
  434. switch (part_num) {
  435. case 0:
  436. mmc->capacity = mmc->capacity_user;
  437. break;
  438. case 1:
  439. case 2:
  440. mmc->capacity = mmc->capacity_boot;
  441. break;
  442. case 3:
  443. mmc->capacity = mmc->capacity_rpmb;
  444. break;
  445. case 4:
  446. case 5:
  447. case 6:
  448. case 7:
  449. mmc->capacity = mmc->capacity_gp[part_num - 4];
  450. break;
  451. default:
  452. return -1;
  453. }
  454. mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
  455. return 0;
  456. }
  457. int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
  458. {
  459. int ret;
  460. ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
  461. (mmc->part_config & ~PART_ACCESS_MASK)
  462. | (part_num & PART_ACCESS_MASK));
  463. /*
  464. * Set the capacity if the switch succeeded or was intended
  465. * to return to representing the raw device.
  466. */
  467. if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
  468. ret = mmc_set_capacity(mmc, part_num);
  469. mmc_get_blk_desc(mmc)->hwpart = part_num;
  470. }
  471. return ret;
  472. }
  473. int mmc_hwpart_config(struct mmc *mmc,
  474. const struct mmc_hwpart_conf *conf,
  475. enum mmc_hwpart_conf_mode mode)
  476. {
  477. u8 part_attrs = 0;
  478. u32 enh_size_mult;
  479. u32 enh_start_addr;
  480. u32 gp_size_mult[4];
  481. u32 max_enh_size_mult;
  482. u32 tot_enh_size_mult = 0;
  483. u8 wr_rel_set;
  484. int i, pidx, err;
  485. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  486. if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
  487. return -EINVAL;
  488. if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
  489. printf("eMMC >= 4.4 required for enhanced user data area\n");
  490. return -EMEDIUMTYPE;
  491. }
  492. if (!(mmc->part_support & PART_SUPPORT)) {
  493. printf("Card does not support partitioning\n");
  494. return -EMEDIUMTYPE;
  495. }
  496. if (!mmc->hc_wp_grp_size) {
  497. printf("Card does not define HC WP group size\n");
  498. return -EMEDIUMTYPE;
  499. }
  500. /* check partition alignment and total enhanced size */
  501. if (conf->user.enh_size) {
  502. if (conf->user.enh_size % mmc->hc_wp_grp_size ||
  503. conf->user.enh_start % mmc->hc_wp_grp_size) {
  504. printf("User data enhanced area not HC WP group "
  505. "size aligned\n");
  506. return -EINVAL;
  507. }
  508. part_attrs |= EXT_CSD_ENH_USR;
  509. enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
  510. if (mmc->high_capacity) {
  511. enh_start_addr = conf->user.enh_start;
  512. } else {
  513. enh_start_addr = (conf->user.enh_start << 9);
  514. }
  515. } else {
  516. enh_size_mult = 0;
  517. enh_start_addr = 0;
  518. }
  519. tot_enh_size_mult += enh_size_mult;
  520. for (pidx = 0; pidx < 4; pidx++) {
  521. if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
  522. printf("GP%i partition not HC WP group size "
  523. "aligned\n", pidx+1);
  524. return -EINVAL;
  525. }
  526. gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
  527. if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
  528. part_attrs |= EXT_CSD_ENH_GP(pidx);
  529. tot_enh_size_mult += gp_size_mult[pidx];
  530. }
  531. }
  532. if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
  533. printf("Card does not support enhanced attribute\n");
  534. return -EMEDIUMTYPE;
  535. }
  536. err = mmc_send_ext_csd(mmc, ext_csd);
  537. if (err)
  538. return err;
  539. max_enh_size_mult =
  540. (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
  541. (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
  542. ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
  543. if (tot_enh_size_mult > max_enh_size_mult) {
  544. printf("Total enhanced size exceeds maximum (%u > %u)\n",
  545. tot_enh_size_mult, max_enh_size_mult);
  546. return -EMEDIUMTYPE;
  547. }
  548. /* The default value of EXT_CSD_WR_REL_SET is device
  549. * dependent, the values can only be changed if the
  550. * EXT_CSD_HS_CTRL_REL bit is set. The values can be
  551. * changed only once and before partitioning is completed. */
  552. wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  553. if (conf->user.wr_rel_change) {
  554. if (conf->user.wr_rel_set)
  555. wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
  556. else
  557. wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
  558. }
  559. for (pidx = 0; pidx < 4; pidx++) {
  560. if (conf->gp_part[pidx].wr_rel_change) {
  561. if (conf->gp_part[pidx].wr_rel_set)
  562. wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
  563. else
  564. wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
  565. }
  566. }
  567. if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
  568. !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
  569. puts("Card does not support host controlled partition write "
  570. "reliability settings\n");
  571. return -EMEDIUMTYPE;
  572. }
  573. if (ext_csd[EXT_CSD_PARTITION_SETTING] &
  574. EXT_CSD_PARTITION_SETTING_COMPLETED) {
  575. printf("Card already partitioned\n");
  576. return -EPERM;
  577. }
  578. if (mode == MMC_HWPART_CONF_CHECK)
  579. return 0;
  580. /* Partitioning requires high-capacity size definitions */
  581. if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
  582. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  583. EXT_CSD_ERASE_GROUP_DEF, 1);
  584. if (err)
  585. return err;
  586. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  587. /* update erase group size to be high-capacity */
  588. mmc->erase_grp_size =
  589. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  590. }
  591. /* all OK, write the configuration */
  592. for (i = 0; i < 4; i++) {
  593. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  594. EXT_CSD_ENH_START_ADDR+i,
  595. (enh_start_addr >> (i*8)) & 0xFF);
  596. if (err)
  597. return err;
  598. }
  599. for (i = 0; i < 3; i++) {
  600. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  601. EXT_CSD_ENH_SIZE_MULT+i,
  602. (enh_size_mult >> (i*8)) & 0xFF);
  603. if (err)
  604. return err;
  605. }
  606. for (pidx = 0; pidx < 4; pidx++) {
  607. for (i = 0; i < 3; i++) {
  608. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  609. EXT_CSD_GP_SIZE_MULT+pidx*3+i,
  610. (gp_size_mult[pidx] >> (i*8)) & 0xFF);
  611. if (err)
  612. return err;
  613. }
  614. }
  615. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  616. EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
  617. if (err)
  618. return err;
  619. if (mode == MMC_HWPART_CONF_SET)
  620. return 0;
  621. /* The WR_REL_SET is a write-once register but shall be
  622. * written before setting PART_SETTING_COMPLETED. As it is
  623. * write-once we can only write it when completing the
  624. * partitioning. */
  625. if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
  626. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  627. EXT_CSD_WR_REL_SET, wr_rel_set);
  628. if (err)
  629. return err;
  630. }
  631. /* Setting PART_SETTING_COMPLETED confirms the partition
  632. * configuration but it only becomes effective after power
  633. * cycle, so we do not adjust the partition related settings
  634. * in the mmc struct. */
  635. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  636. EXT_CSD_PARTITION_SETTING,
  637. EXT_CSD_PARTITION_SETTING_COMPLETED);
  638. if (err)
  639. return err;
  640. return 0;
  641. }
  642. int mmc_getcd(struct mmc *mmc)
  643. {
  644. int cd;
  645. cd = board_mmc_getcd(mmc);
  646. if (cd < 0) {
  647. if (mmc->cfg->ops->getcd)
  648. cd = mmc->cfg->ops->getcd(mmc);
  649. else
  650. cd = 1;
  651. }
  652. return cd;
  653. }
  654. static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
  655. {
  656. struct mmc_cmd cmd;
  657. struct mmc_data data;
  658. /* Switch the frequency */
  659. cmd.cmdidx = SD_CMD_SWITCH_FUNC;
  660. cmd.resp_type = MMC_RSP_R1;
  661. cmd.cmdarg = (mode << 31) | 0xffffff;
  662. cmd.cmdarg &= ~(0xf << (group * 4));
  663. cmd.cmdarg |= value << (group * 4);
  664. data.dest = (char *)resp;
  665. data.blocksize = 64;
  666. data.blocks = 1;
  667. data.flags = MMC_DATA_READ;
  668. return mmc_send_cmd(mmc, &cmd, &data);
  669. }
  670. static int sd_change_freq(struct mmc *mmc)
  671. {
  672. int err;
  673. struct mmc_cmd cmd;
  674. ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
  675. ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
  676. struct mmc_data data;
  677. int timeout;
  678. mmc->card_caps = 0;
  679. if (mmc_host_is_spi(mmc))
  680. return 0;
  681. /* Read the SCR to find out if this card supports higher speeds */
  682. cmd.cmdidx = MMC_CMD_APP_CMD;
  683. cmd.resp_type = MMC_RSP_R1;
  684. cmd.cmdarg = mmc->rca << 16;
  685. err = mmc_send_cmd(mmc, &cmd, NULL);
  686. if (err)
  687. return err;
  688. cmd.cmdidx = SD_CMD_APP_SEND_SCR;
  689. cmd.resp_type = MMC_RSP_R1;
  690. cmd.cmdarg = 0;
  691. timeout = 3;
  692. retry_scr:
  693. data.dest = (char *)scr;
  694. data.blocksize = 8;
  695. data.blocks = 1;
  696. data.flags = MMC_DATA_READ;
  697. err = mmc_send_cmd(mmc, &cmd, &data);
  698. if (err) {
  699. if (timeout--)
  700. goto retry_scr;
  701. return err;
  702. }
  703. mmc->scr[0] = __be32_to_cpu(scr[0]);
  704. mmc->scr[1] = __be32_to_cpu(scr[1]);
  705. switch ((mmc->scr[0] >> 24) & 0xf) {
  706. case 0:
  707. mmc->version = SD_VERSION_1_0;
  708. break;
  709. case 1:
  710. mmc->version = SD_VERSION_1_10;
  711. break;
  712. case 2:
  713. mmc->version = SD_VERSION_2;
  714. if ((mmc->scr[0] >> 15) & 0x1)
  715. mmc->version = SD_VERSION_3;
  716. break;
  717. default:
  718. mmc->version = SD_VERSION_1_0;
  719. break;
  720. }
  721. if (mmc->scr[0] & SD_DATA_4BIT)
  722. mmc->card_caps |= MMC_MODE_4BIT;
  723. /* Version 1.0 doesn't support switching */
  724. if (mmc->version == SD_VERSION_1_0)
  725. return 0;
  726. timeout = 4;
  727. while (timeout--) {
  728. err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
  729. (u8 *)switch_status);
  730. if (err)
  731. return err;
  732. /* The high-speed function is busy. Try again */
  733. if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
  734. break;
  735. }
  736. /* If high-speed isn't supported, we return */
  737. if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
  738. return 0;
  739. /*
  740. * If the host doesn't support SD_HIGHSPEED, do not switch card to
  741. * HIGHSPEED mode even if the card support SD_HIGHSPPED.
  742. * This can avoid furthur problem when the card runs in different
  743. * mode between the host.
  744. */
  745. if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
  746. (mmc->cfg->host_caps & MMC_MODE_HS)))
  747. return 0;
  748. err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
  749. if (err)
  750. return err;
  751. if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
  752. mmc->card_caps |= MMC_MODE_HS;
  753. return 0;
  754. }
  755. /* frequency bases */
  756. /* divided by 10 to be nice to platforms without floating point */
  757. static const int fbase[] = {
  758. 10000,
  759. 100000,
  760. 1000000,
  761. 10000000,
  762. };
  763. /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
  764. * to platforms without floating point.
  765. */
  766. static const u8 multipliers[] = {
  767. 0, /* reserved */
  768. 10,
  769. 12,
  770. 13,
  771. 15,
  772. 20,
  773. 25,
  774. 30,
  775. 35,
  776. 40,
  777. 45,
  778. 50,
  779. 55,
  780. 60,
  781. 70,
  782. 80,
  783. };
  784. static void mmc_set_ios(struct mmc *mmc)
  785. {
  786. if (mmc->cfg->ops->set_ios)
  787. mmc->cfg->ops->set_ios(mmc);
  788. }
  789. void mmc_set_clock(struct mmc *mmc, uint clock)
  790. {
  791. if (clock > mmc->cfg->f_max)
  792. clock = mmc->cfg->f_max;
  793. if (clock < mmc->cfg->f_min)
  794. clock = mmc->cfg->f_min;
  795. mmc->clock = clock;
  796. mmc_set_ios(mmc);
  797. }
  798. static void mmc_set_bus_width(struct mmc *mmc, uint width)
  799. {
  800. mmc->bus_width = width;
  801. mmc_set_ios(mmc);
  802. }
  803. static int mmc_startup(struct mmc *mmc)
  804. {
  805. int err, i;
  806. uint mult, freq;
  807. u64 cmult, csize, capacity;
  808. struct mmc_cmd cmd;
  809. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  810. ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
  811. int timeout = 1000;
  812. bool has_parts = false;
  813. bool part_completed;
  814. struct blk_desc *bdesc;
  815. #ifdef CONFIG_MMC_SPI_CRC_ON
  816. if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
  817. cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
  818. cmd.resp_type = MMC_RSP_R1;
  819. cmd.cmdarg = 1;
  820. err = mmc_send_cmd(mmc, &cmd, NULL);
  821. if (err)
  822. return err;
  823. }
  824. #endif
  825. /* Put the Card in Identify Mode */
  826. cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
  827. MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
  828. cmd.resp_type = MMC_RSP_R2;
  829. cmd.cmdarg = 0;
  830. err = mmc_send_cmd(mmc, &cmd, NULL);
  831. if (err)
  832. return err;
  833. memcpy(mmc->cid, cmd.response, 16);
  834. /*
  835. * For MMC cards, set the Relative Address.
  836. * For SD cards, get the Relatvie Address.
  837. * This also puts the cards into Standby State
  838. */
  839. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  840. cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
  841. cmd.cmdarg = mmc->rca << 16;
  842. cmd.resp_type = MMC_RSP_R6;
  843. err = mmc_send_cmd(mmc, &cmd, NULL);
  844. if (err)
  845. return err;
  846. if (IS_SD(mmc))
  847. mmc->rca = (cmd.response[0] >> 16) & 0xffff;
  848. }
  849. /* Get the Card-Specific Data */
  850. cmd.cmdidx = MMC_CMD_SEND_CSD;
  851. cmd.resp_type = MMC_RSP_R2;
  852. cmd.cmdarg = mmc->rca << 16;
  853. err = mmc_send_cmd(mmc, &cmd, NULL);
  854. /* Waiting for the ready status */
  855. mmc_send_status(mmc, timeout);
  856. if (err)
  857. return err;
  858. mmc->csd[0] = cmd.response[0];
  859. mmc->csd[1] = cmd.response[1];
  860. mmc->csd[2] = cmd.response[2];
  861. mmc->csd[3] = cmd.response[3];
  862. if (mmc->version == MMC_VERSION_UNKNOWN) {
  863. int version = (cmd.response[0] >> 26) & 0xf;
  864. switch (version) {
  865. case 0:
  866. mmc->version = MMC_VERSION_1_2;
  867. break;
  868. case 1:
  869. mmc->version = MMC_VERSION_1_4;
  870. break;
  871. case 2:
  872. mmc->version = MMC_VERSION_2_2;
  873. break;
  874. case 3:
  875. mmc->version = MMC_VERSION_3;
  876. break;
  877. case 4:
  878. mmc->version = MMC_VERSION_4;
  879. break;
  880. default:
  881. mmc->version = MMC_VERSION_1_2;
  882. break;
  883. }
  884. }
  885. /* divide frequency by 10, since the mults are 10x bigger */
  886. freq = fbase[(cmd.response[0] & 0x7)];
  887. mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
  888. mmc->tran_speed = freq * mult;
  889. mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
  890. mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
  891. if (IS_SD(mmc))
  892. mmc->write_bl_len = mmc->read_bl_len;
  893. else
  894. mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
  895. if (mmc->high_capacity) {
  896. csize = (mmc->csd[1] & 0x3f) << 16
  897. | (mmc->csd[2] & 0xffff0000) >> 16;
  898. cmult = 8;
  899. } else {
  900. csize = (mmc->csd[1] & 0x3ff) << 2
  901. | (mmc->csd[2] & 0xc0000000) >> 30;
  902. cmult = (mmc->csd[2] & 0x00038000) >> 15;
  903. }
  904. mmc->capacity_user = (csize + 1) << (cmult + 2);
  905. mmc->capacity_user *= mmc->read_bl_len;
  906. mmc->capacity_boot = 0;
  907. mmc->capacity_rpmb = 0;
  908. for (i = 0; i < 4; i++)
  909. mmc->capacity_gp[i] = 0;
  910. if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
  911. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  912. if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
  913. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  914. if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
  915. cmd.cmdidx = MMC_CMD_SET_DSR;
  916. cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
  917. cmd.resp_type = MMC_RSP_NONE;
  918. if (mmc_send_cmd(mmc, &cmd, NULL))
  919. printf("MMC: SET_DSR failed\n");
  920. }
  921. /* Select the card, and put it into Transfer Mode */
  922. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  923. cmd.cmdidx = MMC_CMD_SELECT_CARD;
  924. cmd.resp_type = MMC_RSP_R1;
  925. cmd.cmdarg = mmc->rca << 16;
  926. err = mmc_send_cmd(mmc, &cmd, NULL);
  927. if (err)
  928. return err;
  929. }
  930. /*
  931. * For SD, its erase group is always one sector
  932. */
  933. mmc->erase_grp_size = 1;
  934. mmc->part_config = MMCPART_NOAVAILABLE;
  935. if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
  936. /* check ext_csd version and capacity */
  937. err = mmc_send_ext_csd(mmc, ext_csd);
  938. if (err)
  939. return err;
  940. if (ext_csd[EXT_CSD_REV] >= 2) {
  941. /*
  942. * According to the JEDEC Standard, the value of
  943. * ext_csd's capacity is valid if the value is more
  944. * than 2GB
  945. */
  946. capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
  947. | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
  948. | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
  949. | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
  950. capacity *= MMC_MAX_BLOCK_LEN;
  951. if ((capacity >> 20) > 2 * 1024)
  952. mmc->capacity_user = capacity;
  953. }
  954. switch (ext_csd[EXT_CSD_REV]) {
  955. case 1:
  956. mmc->version = MMC_VERSION_4_1;
  957. break;
  958. case 2:
  959. mmc->version = MMC_VERSION_4_2;
  960. break;
  961. case 3:
  962. mmc->version = MMC_VERSION_4_3;
  963. break;
  964. case 5:
  965. mmc->version = MMC_VERSION_4_41;
  966. break;
  967. case 6:
  968. mmc->version = MMC_VERSION_4_5;
  969. break;
  970. case 7:
  971. mmc->version = MMC_VERSION_5_0;
  972. break;
  973. case 8:
  974. mmc->version = MMC_VERSION_5_1;
  975. break;
  976. }
  977. /* The partition data may be non-zero but it is only
  978. * effective if PARTITION_SETTING_COMPLETED is set in
  979. * EXT_CSD, so ignore any data if this bit is not set,
  980. * except for enabling the high-capacity group size
  981. * definition (see below). */
  982. part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
  983. EXT_CSD_PARTITION_SETTING_COMPLETED);
  984. /* store the partition info of emmc */
  985. mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
  986. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
  987. ext_csd[EXT_CSD_BOOT_MULT])
  988. mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
  989. if (part_completed &&
  990. (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
  991. mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
  992. mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
  993. mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
  994. for (i = 0; i < 4; i++) {
  995. int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
  996. uint mult = (ext_csd[idx + 2] << 16) +
  997. (ext_csd[idx + 1] << 8) + ext_csd[idx];
  998. if (mult)
  999. has_parts = true;
  1000. if (!part_completed)
  1001. continue;
  1002. mmc->capacity_gp[i] = mult;
  1003. mmc->capacity_gp[i] *=
  1004. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  1005. mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1006. mmc->capacity_gp[i] <<= 19;
  1007. }
  1008. if (part_completed) {
  1009. mmc->enh_user_size =
  1010. (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
  1011. (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
  1012. ext_csd[EXT_CSD_ENH_SIZE_MULT];
  1013. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  1014. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1015. mmc->enh_user_size <<= 19;
  1016. mmc->enh_user_start =
  1017. (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
  1018. (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
  1019. (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
  1020. ext_csd[EXT_CSD_ENH_START_ADDR];
  1021. if (mmc->high_capacity)
  1022. mmc->enh_user_start <<= 9;
  1023. }
  1024. /*
  1025. * Host needs to enable ERASE_GRP_DEF bit if device is
  1026. * partitioned. This bit will be lost every time after a reset
  1027. * or power off. This will affect erase size.
  1028. */
  1029. if (part_completed)
  1030. has_parts = true;
  1031. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
  1032. (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
  1033. has_parts = true;
  1034. if (has_parts) {
  1035. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1036. EXT_CSD_ERASE_GROUP_DEF, 1);
  1037. if (err)
  1038. return err;
  1039. else
  1040. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  1041. }
  1042. if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
  1043. /* Read out group size from ext_csd */
  1044. mmc->erase_grp_size =
  1045. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  1046. /*
  1047. * if high capacity and partition setting completed
  1048. * SEC_COUNT is valid even if it is smaller than 2 GiB
  1049. * JEDEC Standard JESD84-B45, 6.2.4
  1050. */
  1051. if (mmc->high_capacity && part_completed) {
  1052. capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
  1053. (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
  1054. (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
  1055. (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
  1056. capacity *= MMC_MAX_BLOCK_LEN;
  1057. mmc->capacity_user = capacity;
  1058. }
  1059. } else {
  1060. /* Calculate the group size from the csd value. */
  1061. int erase_gsz, erase_gmul;
  1062. erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
  1063. erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
  1064. mmc->erase_grp_size = (erase_gsz + 1)
  1065. * (erase_gmul + 1);
  1066. }
  1067. mmc->hc_wp_grp_size = 1024
  1068. * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  1069. * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1070. mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  1071. }
  1072. err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
  1073. if (err)
  1074. return err;
  1075. if (IS_SD(mmc))
  1076. err = sd_change_freq(mmc);
  1077. else
  1078. err = mmc_change_freq(mmc);
  1079. if (err)
  1080. return err;
  1081. /* Restrict card's capabilities by what the host can do */
  1082. mmc->card_caps &= mmc->cfg->host_caps;
  1083. if (IS_SD(mmc)) {
  1084. if (mmc->card_caps & MMC_MODE_4BIT) {
  1085. cmd.cmdidx = MMC_CMD_APP_CMD;
  1086. cmd.resp_type = MMC_RSP_R1;
  1087. cmd.cmdarg = mmc->rca << 16;
  1088. err = mmc_send_cmd(mmc, &cmd, NULL);
  1089. if (err)
  1090. return err;
  1091. cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
  1092. cmd.resp_type = MMC_RSP_R1;
  1093. cmd.cmdarg = 2;
  1094. err = mmc_send_cmd(mmc, &cmd, NULL);
  1095. if (err)
  1096. return err;
  1097. mmc_set_bus_width(mmc, 4);
  1098. }
  1099. if (mmc->card_caps & MMC_MODE_HS)
  1100. mmc->tran_speed = 50000000;
  1101. else
  1102. mmc->tran_speed = 25000000;
  1103. } else if (mmc->version >= MMC_VERSION_4) {
  1104. /* Only version 4 of MMC supports wider bus widths */
  1105. int idx;
  1106. /* An array of possible bus widths in order of preference */
  1107. static unsigned ext_csd_bits[] = {
  1108. EXT_CSD_DDR_BUS_WIDTH_8,
  1109. EXT_CSD_DDR_BUS_WIDTH_4,
  1110. EXT_CSD_BUS_WIDTH_8,
  1111. EXT_CSD_BUS_WIDTH_4,
  1112. EXT_CSD_BUS_WIDTH_1,
  1113. };
  1114. /* An array to map CSD bus widths to host cap bits */
  1115. static unsigned ext_to_hostcaps[] = {
  1116. [EXT_CSD_DDR_BUS_WIDTH_4] =
  1117. MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
  1118. [EXT_CSD_DDR_BUS_WIDTH_8] =
  1119. MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
  1120. [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
  1121. [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
  1122. };
  1123. /* An array to map chosen bus width to an integer */
  1124. static unsigned widths[] = {
  1125. 8, 4, 8, 4, 1,
  1126. };
  1127. for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
  1128. unsigned int extw = ext_csd_bits[idx];
  1129. unsigned int caps = ext_to_hostcaps[extw];
  1130. /*
  1131. * If the bus width is still not changed,
  1132. * don't try to set the default again.
  1133. * Otherwise, recover from switch attempts
  1134. * by switching to 1-bit bus width.
  1135. */
  1136. if (extw == EXT_CSD_BUS_WIDTH_1 &&
  1137. mmc->bus_width == 1) {
  1138. err = 0;
  1139. break;
  1140. }
  1141. /*
  1142. * Check to make sure the card and controller support
  1143. * these capabilities
  1144. */
  1145. if ((mmc->card_caps & caps) != caps)
  1146. continue;
  1147. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1148. EXT_CSD_BUS_WIDTH, extw);
  1149. if (err)
  1150. continue;
  1151. mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
  1152. mmc_set_bus_width(mmc, widths[idx]);
  1153. err = mmc_send_ext_csd(mmc, test_csd);
  1154. if (err)
  1155. continue;
  1156. /* Only compare read only fields */
  1157. if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
  1158. == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
  1159. ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
  1160. == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
  1161. ext_csd[EXT_CSD_REV]
  1162. == test_csd[EXT_CSD_REV] &&
  1163. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  1164. == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
  1165. memcmp(&ext_csd[EXT_CSD_SEC_CNT],
  1166. &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
  1167. break;
  1168. else
  1169. err = SWITCH_ERR;
  1170. }
  1171. if (err)
  1172. return err;
  1173. if (mmc->card_caps & MMC_MODE_HS) {
  1174. if (mmc->card_caps & MMC_MODE_HS_52MHz)
  1175. mmc->tran_speed = 52000000;
  1176. else
  1177. mmc->tran_speed = 26000000;
  1178. }
  1179. }
  1180. mmc_set_clock(mmc, mmc->tran_speed);
  1181. /* Fix the block length for DDR mode */
  1182. if (mmc->ddr_mode) {
  1183. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  1184. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  1185. }
  1186. /* fill in device description */
  1187. bdesc = mmc_get_blk_desc(mmc);
  1188. bdesc->lun = 0;
  1189. bdesc->hwpart = 0;
  1190. bdesc->type = 0;
  1191. bdesc->blksz = mmc->read_bl_len;
  1192. bdesc->log2blksz = LOG2(bdesc->blksz);
  1193. bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
  1194. #if !defined(CONFIG_SPL_BUILD) || \
  1195. (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
  1196. !defined(CONFIG_USE_TINY_PRINTF))
  1197. sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
  1198. mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
  1199. (mmc->cid[3] >> 16) & 0xffff);
  1200. sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
  1201. (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
  1202. (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
  1203. (mmc->cid[2] >> 24) & 0xff);
  1204. sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
  1205. (mmc->cid[2] >> 16) & 0xf);
  1206. #else
  1207. bdesc->vendor[0] = 0;
  1208. bdesc->product[0] = 0;
  1209. bdesc->revision[0] = 0;
  1210. #endif
  1211. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
  1212. part_init(bdesc);
  1213. #endif
  1214. return 0;
  1215. }
  1216. static int mmc_send_if_cond(struct mmc *mmc)
  1217. {
  1218. struct mmc_cmd cmd;
  1219. int err;
  1220. cmd.cmdidx = SD_CMD_SEND_IF_COND;
  1221. /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
  1222. cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
  1223. cmd.resp_type = MMC_RSP_R7;
  1224. err = mmc_send_cmd(mmc, &cmd, NULL);
  1225. if (err)
  1226. return err;
  1227. if ((cmd.response[0] & 0xff) != 0xaa)
  1228. return UNUSABLE_ERR;
  1229. else
  1230. mmc->version = SD_VERSION_2;
  1231. return 0;
  1232. }
  1233. /* board-specific MMC power initializations. */
  1234. __weak void board_mmc_power_init(void)
  1235. {
  1236. }
  1237. int mmc_start_init(struct mmc *mmc)
  1238. {
  1239. int err;
  1240. /* we pretend there's no card when init is NULL */
  1241. if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
  1242. mmc->has_init = 0;
  1243. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  1244. printf("MMC: no card present\n");
  1245. #endif
  1246. return NO_CARD_ERR;
  1247. }
  1248. if (mmc->has_init)
  1249. return 0;
  1250. #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  1251. mmc_adapter_card_type_ident();
  1252. #endif
  1253. board_mmc_power_init();
  1254. /* made sure it's not NULL earlier */
  1255. err = mmc->cfg->ops->init(mmc);
  1256. if (err)
  1257. return err;
  1258. mmc->ddr_mode = 0;
  1259. mmc_set_bus_width(mmc, 1);
  1260. mmc_set_clock(mmc, 1);
  1261. /* Reset the Card */
  1262. err = mmc_go_idle(mmc);
  1263. if (err)
  1264. return err;
  1265. /* The internal partition reset to user partition(0) at every CMD0*/
  1266. mmc_get_blk_desc(mmc)->hwpart = 0;
  1267. /* Test for SD version 2 */
  1268. err = mmc_send_if_cond(mmc);
  1269. /* Now try to get the SD card's operating condition */
  1270. err = sd_send_op_cond(mmc);
  1271. /* If the command timed out, we check for an MMC card */
  1272. if (err == TIMEOUT) {
  1273. err = mmc_send_op_cond(mmc);
  1274. if (err) {
  1275. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  1276. printf("Card did not respond to voltage select!\n");
  1277. #endif
  1278. return UNUSABLE_ERR;
  1279. }
  1280. }
  1281. if (!err)
  1282. mmc->init_in_progress = 1;
  1283. return err;
  1284. }
  1285. static int mmc_complete_init(struct mmc *mmc)
  1286. {
  1287. int err = 0;
  1288. mmc->init_in_progress = 0;
  1289. if (mmc->op_cond_pending)
  1290. err = mmc_complete_op_cond(mmc);
  1291. if (!err)
  1292. err = mmc_startup(mmc);
  1293. if (err)
  1294. mmc->has_init = 0;
  1295. else
  1296. mmc->has_init = 1;
  1297. return err;
  1298. }
  1299. int mmc_init(struct mmc *mmc)
  1300. {
  1301. int err = 0;
  1302. unsigned start;
  1303. #ifdef CONFIG_DM_MMC
  1304. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
  1305. upriv->mmc = mmc;
  1306. #endif
  1307. if (mmc->has_init)
  1308. return 0;
  1309. start = get_timer(0);
  1310. if (!mmc->init_in_progress)
  1311. err = mmc_start_init(mmc);
  1312. if (!err)
  1313. err = mmc_complete_init(mmc);
  1314. debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
  1315. return err;
  1316. }
  1317. int mmc_set_dsr(struct mmc *mmc, u16 val)
  1318. {
  1319. mmc->dsr = val;
  1320. return 0;
  1321. }
  1322. /* CPU-specific MMC initializations */
  1323. __weak int cpu_mmc_init(bd_t *bis)
  1324. {
  1325. return -1;
  1326. }
  1327. /* board-specific MMC initializations. */
  1328. __weak int board_mmc_init(bd_t *bis)
  1329. {
  1330. return -1;
  1331. }
  1332. void mmc_set_preinit(struct mmc *mmc, int preinit)
  1333. {
  1334. mmc->preinit = preinit;
  1335. }
  1336. #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
  1337. static int mmc_probe(bd_t *bis)
  1338. {
  1339. return 0;
  1340. }
  1341. #elif defined(CONFIG_DM_MMC)
  1342. static int mmc_probe(bd_t *bis)
  1343. {
  1344. int ret, i;
  1345. struct uclass *uc;
  1346. struct udevice *dev;
  1347. ret = uclass_get(UCLASS_MMC, &uc);
  1348. if (ret)
  1349. return ret;
  1350. /*
  1351. * Try to add them in sequence order. Really with driver model we
  1352. * should allow holes, but the current MMC list does not allow that.
  1353. * So if we request 0, 1, 3 we will get 0, 1, 2.
  1354. */
  1355. for (i = 0; ; i++) {
  1356. ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
  1357. if (ret == -ENODEV)
  1358. break;
  1359. }
  1360. uclass_foreach_dev(dev, uc) {
  1361. ret = device_probe(dev);
  1362. if (ret)
  1363. printf("%s - probe failed: %d\n", dev->name, ret);
  1364. }
  1365. return 0;
  1366. }
  1367. #else
  1368. static int mmc_probe(bd_t *bis)
  1369. {
  1370. if (board_mmc_init(bis) < 0)
  1371. cpu_mmc_init(bis);
  1372. return 0;
  1373. }
  1374. #endif
  1375. int mmc_initialize(bd_t *bis)
  1376. {
  1377. static int initialized = 0;
  1378. int ret;
  1379. if (initialized) /* Avoid initializing mmc multiple times */
  1380. return 0;
  1381. initialized = 1;
  1382. #ifndef CONFIG_BLK
  1383. mmc_list_init();
  1384. #endif
  1385. ret = mmc_probe(bis);
  1386. if (ret)
  1387. return ret;
  1388. #ifndef CONFIG_SPL_BUILD
  1389. print_mmc_devices(',');
  1390. #endif
  1391. mmc_do_preinit();
  1392. return 0;
  1393. }