i2c.c 10 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #ifdef CONFIG_HARD_I2C
  26. #include <mpc5xxx.h>
  27. #include <i2c.h>
  28. #if !defined(CONFIG_I2C_MULTI_BUS)
  29. #if (CONFIG_SYS_I2C_MODULE == 2)
  30. #define I2C_BASE MPC5XXX_I2C2
  31. #elif (CONFIG_SYS_I2C_MODULE == 1)
  32. #define I2C_BASE MPC5XXX_I2C1
  33. #else
  34. #error CONFIG_SYS_I2C_MODULE is not properly configured
  35. #endif
  36. #else
  37. static unsigned int i2c_bus_num __attribute__ ((section (".data"))) =
  38. CONFIG_SYS_SPD_BUS_NUM;
  39. static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED,
  40. CONFIG_SYS_I2C_SPEED};
  41. static const unsigned long i2c_dev[2] = {
  42. MPC5XXX_I2C1,
  43. MPC5XXX_I2C2,
  44. };
  45. #define I2C_BASE ((struct mpc5xxx_i2c *)i2c_dev[i2c_bus_num])
  46. #endif
  47. #define I2C_TIMEOUT 6667
  48. #define I2C_RETRIES 3
  49. struct mpc5xxx_i2c_tap {
  50. int scl2tap;
  51. int tap2tap;
  52. };
  53. static int mpc_reg_in (volatile u32 *reg);
  54. static void mpc_reg_out (volatile u32 *reg, int val, int mask);
  55. static int wait_for_bb (void);
  56. static int wait_for_pin (int *status);
  57. static int do_address (uchar chip, char rdwr_flag);
  58. static int send_bytes (uchar chip, char *buf, int len);
  59. static int receive_bytes (uchar chip, char *buf, int len);
  60. static int mpc_get_fdr (int);
  61. static int mpc_reg_in(volatile u32 *reg)
  62. {
  63. int ret = *reg >> 24;
  64. __asm__ __volatile__ ("eieio");
  65. return ret;
  66. }
  67. static void mpc_reg_out(volatile u32 *reg, int val, int mask)
  68. {
  69. int tmp;
  70. if (!mask) {
  71. *reg = val << 24;
  72. } else {
  73. tmp = mpc_reg_in(reg);
  74. *reg = ((tmp & ~mask) | (val & mask)) << 24;
  75. }
  76. __asm__ __volatile__ ("eieio");
  77. return;
  78. }
  79. static int wait_for_bb(void)
  80. {
  81. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  82. int timeout = I2C_TIMEOUT;
  83. int status;
  84. status = mpc_reg_in(&regs->msr);
  85. while (timeout-- && (status & I2C_BB)) {
  86. #if 1
  87. volatile int temp;
  88. mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
  89. temp = mpc_reg_in(&regs->mdr);
  90. mpc_reg_out(&regs->mcr, 0, I2C_STA);
  91. mpc_reg_out(&regs->mcr, 0, 0);
  92. mpc_reg_out(&regs->mcr, I2C_EN, 0);
  93. #endif
  94. udelay(15);
  95. status = mpc_reg_in(&regs->msr);
  96. }
  97. return (status & I2C_BB);
  98. }
  99. static int wait_for_pin(int *status)
  100. {
  101. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  102. int timeout = I2C_TIMEOUT;
  103. *status = mpc_reg_in(&regs->msr);
  104. while (timeout-- && !(*status & I2C_IF)) {
  105. udelay(15);
  106. *status = mpc_reg_in(&regs->msr);
  107. }
  108. if (!(*status & I2C_IF)) {
  109. return -1;
  110. }
  111. mpc_reg_out(&regs->msr, 0, I2C_IF);
  112. return 0;
  113. }
  114. static int do_address(uchar chip, char rdwr_flag)
  115. {
  116. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  117. int status;
  118. chip <<= 1;
  119. if (rdwr_flag) {
  120. chip |= 1;
  121. }
  122. mpc_reg_out(&regs->mcr, I2C_TX, I2C_TX);
  123. mpc_reg_out(&regs->mdr, chip, 0);
  124. if (wait_for_pin(&status)) {
  125. return -2;
  126. }
  127. if (status & I2C_RXAK) {
  128. return -3;
  129. }
  130. return 0;
  131. }
  132. static int send_bytes(uchar chip, char *buf, int len)
  133. {
  134. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  135. int wrcount;
  136. int status;
  137. for (wrcount = 0; wrcount < len; ++wrcount) {
  138. mpc_reg_out(&regs->mdr, buf[wrcount], 0);
  139. if (wait_for_pin(&status)) {
  140. break;
  141. }
  142. if (status & I2C_RXAK) {
  143. break;
  144. }
  145. }
  146. return !(wrcount == len);
  147. }
  148. static int receive_bytes(uchar chip, char *buf, int len)
  149. {
  150. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  151. int dummy = 1;
  152. int rdcount = 0;
  153. int status;
  154. int i;
  155. mpc_reg_out(&regs->mcr, 0, I2C_TX);
  156. for (i = 0; i < len; ++i) {
  157. buf[rdcount] = mpc_reg_in(&regs->mdr);
  158. if (dummy) {
  159. dummy = 0;
  160. } else {
  161. rdcount++;
  162. }
  163. if (wait_for_pin(&status)) {
  164. return -4;
  165. }
  166. }
  167. mpc_reg_out(&regs->mcr, I2C_TXAK, I2C_TXAK);
  168. buf[rdcount++] = mpc_reg_in(&regs->mdr);
  169. if (wait_for_pin(&status)) {
  170. return -5;
  171. }
  172. mpc_reg_out(&regs->mcr, 0, I2C_TXAK);
  173. return 0;
  174. }
  175. #if defined(CONFIG_SYS_I2C_INIT_MPC5XXX)
  176. #define FDR510(x) (u8) (((x & 0x20) >> 3) | (x & 0x3))
  177. #define FDR432(x) (u8) ((x & 0x1C) >> 2)
  178. /*
  179. * Reset any i2c devices that may have been interrupted during a system reset.
  180. * Normally this would be accomplished by clocking the line until SCL and SDA
  181. * are released and then sending a start condtiion (From an Atmel datasheet).
  182. * There is no direct access to the i2c pins so instead create start commands
  183. * through the i2c interface. Send a start command then delay for the SDA Hold
  184. * time, repeat this by disabling/enabling the bus a total of 9 times.
  185. */
  186. static void send_reset(void)
  187. {
  188. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  189. int i;
  190. u32 delay;
  191. u8 fdr;
  192. int SDA_Tap[] = { 3, 3, 4, 4, 1, 1, 2, 2};
  193. struct mpc5xxx_i2c_tap scltap[] = {
  194. {4, 1},
  195. {4, 2},
  196. {6, 4},
  197. {6, 8},
  198. {14, 16},
  199. {30, 32},
  200. {62, 64},
  201. {126, 128}
  202. };
  203. fdr = (u8)mpc_reg_in(&regs->mfdr);
  204. delay = scltap[FDR432(fdr)].scl2tap + ((SDA_Tap[FDR510(fdr)] - 1) * \
  205. scltap[FDR432(fdr)].tap2tap) + 3;
  206. for (i = 0; i < 9; i++) {
  207. mpc_reg_out(&regs->mcr, I2C_EN|I2C_STA|I2C_TX, I2C_INIT_MASK);
  208. udelay(delay);
  209. mpc_reg_out(&regs->mcr, 0, I2C_INIT_MASK);
  210. udelay(delay);
  211. }
  212. mpc_reg_out(&regs->mcr, I2C_EN, I2C_INIT_MASK);
  213. }
  214. #endif /* CONFIG_SYS_I2c_INIT_MPC5XXX */
  215. /**************** I2C API ****************/
  216. void i2c_init(int speed, int saddr)
  217. {
  218. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  219. mpc_reg_out(&regs->mcr, 0, 0);
  220. mpc_reg_out(&regs->madr, saddr << 1, 0);
  221. /* Set clock
  222. */
  223. mpc_reg_out(&regs->mfdr, mpc_get_fdr(speed), 0);
  224. /* Enable module
  225. */
  226. mpc_reg_out(&regs->mcr, I2C_EN, I2C_INIT_MASK);
  227. mpc_reg_out(&regs->msr, 0, I2C_IF);
  228. #if defined(CONFIG_SYS_I2C_INIT_MPC5XXX)
  229. send_reset();
  230. #endif
  231. return;
  232. }
  233. static int mpc_get_fdr(int speed)
  234. {
  235. static int fdr = -1;
  236. if (fdr == -1) {
  237. ulong best_speed = 0;
  238. ulong divider;
  239. ulong ipb, scl;
  240. ulong bestmatch = 0xffffffffUL;
  241. int best_i = 0, best_j = 0, i, j;
  242. int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8};
  243. struct mpc5xxx_i2c_tap scltap[] = {
  244. {4, 1},
  245. {4, 2},
  246. {6, 4},
  247. {6, 8},
  248. {14, 16},
  249. {30, 32},
  250. {62, 64},
  251. {126, 128}
  252. };
  253. ipb = gd->ipb_clk;
  254. for (i = 7; i >= 0; i--) {
  255. for (j = 7; j >= 0; j--) {
  256. scl = 2 * (scltap[j].scl2tap +
  257. (SCL_Tap[i] - 1) * scltap[j].tap2tap + 2);
  258. if (ipb <= speed*scl) {
  259. if ((speed*scl - ipb) < bestmatch) {
  260. bestmatch = speed*scl - ipb;
  261. best_i = i;
  262. best_j = j;
  263. best_speed = ipb/scl;
  264. }
  265. }
  266. }
  267. }
  268. divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2);
  269. if (gd->flags & GD_FLG_RELOC) {
  270. fdr = divider;
  271. } else {
  272. if (gd->have_console)
  273. printf("%ld kHz, ", best_speed / 1000);
  274. return divider;
  275. }
  276. }
  277. return fdr;
  278. }
  279. int i2c_probe(uchar chip)
  280. {
  281. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  282. int i;
  283. for (i = 0; i < I2C_RETRIES; i++) {
  284. mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
  285. if (! do_address(chip, 0)) {
  286. mpc_reg_out(&regs->mcr, 0, I2C_STA);
  287. udelay(500);
  288. break;
  289. }
  290. mpc_reg_out(&regs->mcr, 0, I2C_STA);
  291. udelay(500);
  292. }
  293. return (i == I2C_RETRIES);
  294. }
  295. int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
  296. {
  297. char xaddr[4];
  298. struct mpc5xxx_i2c * regs = (struct mpc5xxx_i2c *)I2C_BASE;
  299. int ret = -1;
  300. xaddr[0] = (addr >> 24) & 0xFF;
  301. xaddr[1] = (addr >> 16) & 0xFF;
  302. xaddr[2] = (addr >> 8) & 0xFF;
  303. xaddr[3] = addr & 0xFF;
  304. if (wait_for_bb()) {
  305. if (gd->have_console)
  306. printf("i2c_read: bus is busy\n");
  307. goto Done;
  308. }
  309. mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
  310. if (do_address(chip, 0)) {
  311. if (gd->have_console)
  312. printf("i2c_read: failed to address chip\n");
  313. goto Done;
  314. }
  315. if (send_bytes(chip, &xaddr[4-alen], alen)) {
  316. if (gd->have_console)
  317. printf("i2c_read: send_bytes failed\n");
  318. goto Done;
  319. }
  320. mpc_reg_out(&regs->mcr, I2C_RSTA, I2C_RSTA);
  321. if (do_address(chip, 1)) {
  322. if (gd->have_console)
  323. printf("i2c_read: failed to address chip\n");
  324. goto Done;
  325. }
  326. if (receive_bytes(chip, (char *)buf, len)) {
  327. if (gd->have_console)
  328. printf("i2c_read: receive_bytes failed\n");
  329. goto Done;
  330. }
  331. ret = 0;
  332. Done:
  333. mpc_reg_out(&regs->mcr, 0, I2C_STA);
  334. return ret;
  335. }
  336. int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
  337. {
  338. char xaddr[4];
  339. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  340. int ret = -1;
  341. xaddr[0] = (addr >> 24) & 0xFF;
  342. xaddr[1] = (addr >> 16) & 0xFF;
  343. xaddr[2] = (addr >> 8) & 0xFF;
  344. xaddr[3] = addr & 0xFF;
  345. if (wait_for_bb()) {
  346. if (gd->have_console)
  347. printf("i2c_write: bus is busy\n");
  348. goto Done;
  349. }
  350. mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
  351. if (do_address(chip, 0)) {
  352. if (gd->have_console)
  353. printf("i2c_write: failed to address chip\n");
  354. goto Done;
  355. }
  356. if (send_bytes(chip, &xaddr[4-alen], alen)) {
  357. if (gd->have_console)
  358. printf("i2c_write: send_bytes failed\n");
  359. goto Done;
  360. }
  361. if (send_bytes(chip, (char *)buf, len)) {
  362. if (gd->have_console)
  363. printf("i2c_write: send_bytes failed\n");
  364. goto Done;
  365. }
  366. ret = 0;
  367. Done:
  368. mpc_reg_out(&regs->mcr, 0, I2C_STA);
  369. return ret;
  370. }
  371. #if defined(CONFIG_I2C_MULTI_BUS)
  372. int i2c_set_bus_num(unsigned int bus)
  373. {
  374. if (bus > 1)
  375. return -1;
  376. i2c_bus_num = bus;
  377. i2c_init(i2c_bus_speed[bus], CONFIG_SYS_I2C_SLAVE);
  378. return 0;
  379. }
  380. int i2c_set_bus_speed(unsigned int speed)
  381. {
  382. i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
  383. return 0;
  384. }
  385. unsigned int i2c_get_bus_num(void)
  386. {
  387. return i2c_bus_num;
  388. }
  389. unsigned int i2c_get_bus_speed(void)
  390. {
  391. return i2c_bus_speed[i2c_bus_num];
  392. }
  393. #endif
  394. #endif /* CONFIG_HARD_I2C */