Kconfig 9.9 KB

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  1. #
  2. # Multifunction miscellaneous devices
  3. #
  4. menu "Multifunction device drivers"
  5. config MISC
  6. bool "Enable Driver Model for Misc drivers"
  7. depends on DM
  8. help
  9. Enable driver model for miscellaneous devices. This class is
  10. used only for those do not fit other more general classes. A
  11. set of generic read, write and ioctl methods may be used to
  12. access the device.
  13. config ALTERA_SYSID
  14. bool "Altera Sysid support"
  15. depends on MISC
  16. help
  17. Select this to enable a sysid for Altera devices. Please find
  18. details on the "Embedded Peripherals IP User Guide" of Altera.
  19. config ATSHA204A
  20. bool "Support for Atmel ATSHA204A module"
  21. depends on MISC
  22. help
  23. Enable support for I2C connected Atmel's ATSHA204A
  24. CryptoAuthentication module found for example on the Turris Omnia
  25. board.
  26. config ROCKCHIP_EFUSE
  27. bool "Rockchip e-fuse support"
  28. depends on MISC
  29. help
  30. Enable (read-only) access for the e-fuse block found in Rockchip
  31. SoCs: accesses can either be made using byte addressing and a length
  32. or through child-nodes that are generated based on the e-fuse map
  33. retrieved from the DTS.
  34. This driver currently supports the RK3399 only, but can easily be
  35. extended (by porting the read function from the Linux kernel sources)
  36. to support other recent Rockchip devices.
  37. config VEXPRESS_CONFIG
  38. bool "Enable support for Arm Versatile Express config bus"
  39. depends on MISC
  40. help
  41. If you say Y here, you will get support for accessing the
  42. configuration bus on the Arm Versatile Express boards via
  43. a sysreg driver.
  44. config CMD_CROS_EC
  45. bool "Enable crosec command"
  46. depends on CROS_EC
  47. help
  48. Enable command-line access to the Chrome OS EC (Embedded
  49. Controller). This provides the 'crosec' command which has
  50. a number of sub-commands for performing EC tasks such as
  51. updating its flash, accessing a small saved context area
  52. and talking to the I2C bus behind the EC (if there is one).
  53. config CROS_EC
  54. bool "Enable Chrome OS EC"
  55. help
  56. Enable access to the Chrome OS EC. This is a separate
  57. microcontroller typically available on a SPI bus on Chromebooks. It
  58. provides access to the keyboard, some internal storage and may
  59. control access to the battery and main PMIC depending on the
  60. device. You can use the 'crosec' command to access it.
  61. config CROS_EC_I2C
  62. bool "Enable Chrome OS EC I2C driver"
  63. depends on CROS_EC
  64. help
  65. Enable I2C access to the Chrome OS EC. This is used on older
  66. ARM Chromebooks such as snow and spring before the standard bus
  67. changed to SPI. The EC will accept commands across the I2C using
  68. a special message protocol, and provide responses.
  69. config CROS_EC_LPC
  70. bool "Enable Chrome OS EC LPC driver"
  71. depends on CROS_EC
  72. help
  73. Enable I2C access to the Chrome OS EC. This is used on x86
  74. Chromebooks such as link and falco. The keyboard is provided
  75. through a legacy port interface, so on x86 machines the main
  76. function of the EC is power and thermal management.
  77. config CROS_EC_SANDBOX
  78. bool "Enable Chrome OS EC sandbox driver"
  79. depends on CROS_EC && SANDBOX
  80. help
  81. Enable a sandbox emulation of the Chrome OS EC. This supports
  82. keyboard (use the -l flag to enable the LCD), verified boot context,
  83. EC flash read/write/erase support and a few other things. It is
  84. enough to perform a Chrome OS verified boot on sandbox.
  85. config CROS_EC_SPI
  86. bool "Enable Chrome OS EC SPI driver"
  87. depends on CROS_EC
  88. help
  89. Enable SPI access to the Chrome OS EC. This is used on newer
  90. ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
  91. provides a faster and more robust interface than I2C but the bugs
  92. are less interesting.
  93. config DS4510
  94. bool "Enable support for DS4510 CPU supervisor"
  95. help
  96. Enable support for the Maxim DS4510 CPU supervisor. It has an
  97. integrated 64-byte EEPROM, four programmable non-volatile I/O pins
  98. and a configurable timer for the supervisor function. The device is
  99. connected over I2C.
  100. config FSL_SEC_MON
  101. bool "Enable FSL SEC_MON Driver"
  102. help
  103. Freescale Security Monitor block is responsible for monitoring
  104. system states.
  105. Security Monitor can be transitioned on any security failures,
  106. like software violations or hardware security violations.
  107. config MXC_OCOTP
  108. bool "Enable MXC OCOTP Driver"
  109. help
  110. If you say Y here, you will get support for the One Time
  111. Programmable memory pages that are stored on the some
  112. Freescale i.MX processors.
  113. config NUVOTON_NCT6102D
  114. bool "Enable Nuvoton NCT6102D Super I/O driver"
  115. help
  116. If you say Y here, you will get support for the Nuvoton
  117. NCT6102D Super I/O driver. This can be used to enable or
  118. disable the legacy UART, the watchdog or other devices
  119. in the Nuvoton Super IO chips on X86 platforms.
  120. config PWRSEQ
  121. bool "Enable power-sequencing drivers"
  122. depends on DM
  123. help
  124. Power-sequencing drivers provide support for controlling power for
  125. devices. They are typically referenced by a phandle from another
  126. device. When the device is started up, its power sequence can be
  127. initiated.
  128. config SPL_PWRSEQ
  129. bool "Enable power-sequencing drivers for SPL"
  130. depends on PWRSEQ
  131. help
  132. Power-sequencing drivers provide support for controlling power for
  133. devices. They are typically referenced by a phandle from another
  134. device. When the device is started up, its power sequence can be
  135. initiated.
  136. config PCA9551_LED
  137. bool "Enable PCA9551 LED driver"
  138. help
  139. Enable driver for PCA9551 LED controller. This controller
  140. is connected via I2C. So I2C needs to be enabled.
  141. config PCA9551_I2C_ADDR
  142. hex "I2C address of PCA9551 LED controller"
  143. depends on PCA9551_LED
  144. default 0x60
  145. help
  146. The I2C address of the PCA9551 LED controller.
  147. config STM32MP_FUSE
  148. bool "Enable STM32MP fuse wrapper providing the fuse API"
  149. depends on ARCH_STM32MP && MISC
  150. default y if CMD_FUSE
  151. help
  152. If you say Y here, you will get support for the fuse API (OTP)
  153. for STM32MP architecture.
  154. This API is needed for CMD_FUSE.
  155. config STM32_RCC
  156. bool "Enable RCC driver for the STM32 SoC's family"
  157. depends on (STM32 || ARCH_STM32MP) && MISC
  158. help
  159. Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
  160. block) is responsible of the management of the clock and reset
  161. generation.
  162. This driver is similar to an MFD driver in the Linux kernel.
  163. config TEGRA_CAR
  164. bool "Enable support for the Tegra CAR driver"
  165. depends on TEGRA_NO_BPMP
  166. help
  167. The Tegra CAR (Clock and Reset Controller) is a HW module that
  168. controls almost all clocks and resets in a Tegra SoC.
  169. config TEGRA186_BPMP
  170. bool "Enable support for the Tegra186 BPMP driver"
  171. depends on TEGRA186
  172. help
  173. The Tegra BPMP (Boot and Power Management Processor) is a separate
  174. auxiliary CPU embedded into Tegra to perform power management work,
  175. and controls related features such as clocks, resets, power domains,
  176. PMIC I2C bus, etc. This driver provides the core low-level
  177. communication path by which feature-specific drivers (such as clock)
  178. can make requests to the BPMP. This driver is similar to an MFD
  179. driver in the Linux kernel.
  180. config TWL4030_LED
  181. bool "Enable TWL4030 LED controller"
  182. help
  183. Enable this to add support for the TWL4030 LED controller.
  184. config WINBOND_W83627
  185. bool "Enable Winbond Super I/O driver"
  186. help
  187. If you say Y here, you will get support for the Winbond
  188. W83627 Super I/O driver. This can be used to enable the
  189. legacy UART or other devices in the Winbond Super IO chips
  190. on X86 platforms.
  191. config QFW
  192. bool
  193. help
  194. Hidden option to enable QEMU fw_cfg interface. This will be selected by
  195. either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
  196. config I2C_EEPROM
  197. bool "Enable driver for generic I2C-attached EEPROMs"
  198. depends on MISC
  199. help
  200. Enable a generic driver for EEPROMs attached via I2C.
  201. config SPL_I2C_EEPROM
  202. bool "Enable driver for generic I2C-attached EEPROMs for SPL"
  203. depends on MISC && SPL && SPL_DM
  204. help
  205. This option is an SPL-variant of the I2C_EEPROM option.
  206. See the help of I2C_EEPROM for details.
  207. config ZYNQ_GEM_I2C_MAC_OFFSET
  208. hex "Set the I2C MAC offset"
  209. default 0x0
  210. help
  211. Set the MAC offset for i2C.
  212. if I2C_EEPROM
  213. config SYS_I2C_EEPROM_ADDR
  214. hex "Chip address of the EEPROM device"
  215. default 0
  216. config SYS_I2C_EEPROM_BUS
  217. int "I2C bus of the EEPROM device."
  218. default 0
  219. config SYS_EEPROM_SIZE
  220. int "Size in bytes of the EEPROM device"
  221. default 256
  222. config SYS_EEPROM_PAGE_WRITE_BITS
  223. int "Number of bits used to address bytes in a single page"
  224. default 0
  225. help
  226. The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
  227. A 64 byte page, for example would require six bits.
  228. config SYS_EEPROM_PAGE_WRITE_DELAY_MS
  229. int "Number of milliseconds to delay between page writes"
  230. default 0
  231. config SYS_I2C_EEPROM_ADDR_LEN
  232. int "Length in bytes of the EEPROM memory array address"
  233. default 1
  234. help
  235. Note: This is NOT the chip address length!
  236. config SYS_I2C_EEPROM_ADDR_OVERFLOW
  237. hex "EEPROM Address Overflow"
  238. default 0
  239. help
  240. EEPROM chips that implement "address overflow" are ones
  241. like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  242. address and the extra bits end up in the "chip address" bit
  243. slots. This makes a 24WC08 (1Kbyte) chip look like four 256
  244. byte chips.
  245. endif
  246. config GDSYS_RXAUI_CTRL
  247. bool "Enable gdsys RXAUI control driver"
  248. depends on MISC
  249. help
  250. Support gdsys FPGA's RXAUI control.
  251. config GDSYS_IOEP
  252. bool "Enable gdsys IOEP driver"
  253. depends on MISC
  254. help
  255. Support gdsys FPGA's IO endpoint driver.
  256. config MPC83XX_SERDES
  257. bool "Enable MPC83xx serdes driver"
  258. depends on MISC
  259. help
  260. Support for serdes found on MPC83xx SoCs.
  261. config FS_LOADER
  262. bool "Enable loader driver for file system"
  263. help
  264. This is file system generic loader which can be used to load
  265. the file image from the storage into target such as memory.
  266. The consumer driver would then use this loader to program whatever,
  267. ie. the FPGA device.
  268. config GDSYS_SOC
  269. bool "Enable gdsys SOC driver"
  270. depends on MISC
  271. help
  272. Support for gdsys IHS SOC, a simple bus associated with each gdsys
  273. IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
  274. register maps are contained within the FPGA's register map.
  275. endmenu