clock-tables.h 3.3 KB

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  1. /*
  2. * Copyright (c) 2011 The Chromium OS Authors.
  3. * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /* Tegra20 clock PLL tables */
  8. #ifndef _CLOCK_TABLES_H_
  9. #define _CLOCK_TABLES_H_
  10. /* The PLLs supported by the hardware */
  11. enum clock_id {
  12. CLOCK_ID_FIRST,
  13. CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
  14. CLOCK_ID_MEMORY,
  15. CLOCK_ID_PERIPH,
  16. CLOCK_ID_AUDIO,
  17. CLOCK_ID_USB,
  18. CLOCK_ID_DISPLAY,
  19. /* now the simple ones */
  20. CLOCK_ID_FIRST_SIMPLE,
  21. CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
  22. CLOCK_ID_EPCI,
  23. CLOCK_ID_SFROM32KHZ,
  24. /* These are the base clocks (inputs to the Tegra SOC) */
  25. CLOCK_ID_32KHZ,
  26. CLOCK_ID_OSC,
  27. CLOCK_ID_CLK_M,
  28. CLOCK_ID_COUNT, /* number of clocks */
  29. CLOCK_ID_NONE = -1,
  30. };
  31. /* The clocks supported by the hardware */
  32. enum periph_id {
  33. PERIPH_ID_FIRST,
  34. /* Low word: 31:0 */
  35. PERIPH_ID_CPU = PERIPH_ID_FIRST,
  36. PERIPH_ID_RESERVED1,
  37. PERIPH_ID_RESERVED2,
  38. PERIPH_ID_AC97,
  39. PERIPH_ID_RTC,
  40. PERIPH_ID_TMR,
  41. PERIPH_ID_UART1,
  42. PERIPH_ID_UART2,
  43. /* 8 */
  44. PERIPH_ID_GPIO,
  45. PERIPH_ID_SDMMC2,
  46. PERIPH_ID_SPDIF,
  47. PERIPH_ID_I2S1,
  48. PERIPH_ID_I2C1,
  49. PERIPH_ID_NDFLASH,
  50. PERIPH_ID_SDMMC1,
  51. PERIPH_ID_SDMMC4,
  52. /* 16 */
  53. PERIPH_ID_TWC,
  54. PERIPH_ID_PWM,
  55. PERIPH_ID_I2S2,
  56. PERIPH_ID_EPP,
  57. PERIPH_ID_VI,
  58. PERIPH_ID_2D,
  59. PERIPH_ID_USBD,
  60. PERIPH_ID_ISP,
  61. /* 24 */
  62. PERIPH_ID_3D,
  63. PERIPH_ID_IDE,
  64. PERIPH_ID_DISP2,
  65. PERIPH_ID_DISP1,
  66. PERIPH_ID_HOST1X,
  67. PERIPH_ID_VCP,
  68. PERIPH_ID_RESERVED30,
  69. PERIPH_ID_CACHE2,
  70. /* Middle word: 63:32 */
  71. PERIPH_ID_MEM,
  72. PERIPH_ID_AHBDMA,
  73. PERIPH_ID_APBDMA,
  74. PERIPH_ID_RESERVED35,
  75. PERIPH_ID_KBC,
  76. PERIPH_ID_STAT_MON,
  77. PERIPH_ID_PMC,
  78. PERIPH_ID_FUSE,
  79. /* 40 */
  80. PERIPH_ID_KFUSE,
  81. PERIPH_ID_SBC1,
  82. PERIPH_ID_SNOR,
  83. PERIPH_ID_SPI1,
  84. PERIPH_ID_SBC2,
  85. PERIPH_ID_XIO,
  86. PERIPH_ID_SBC3,
  87. PERIPH_ID_DVC_I2C,
  88. /* 48 */
  89. PERIPH_ID_DSI,
  90. PERIPH_ID_TVO,
  91. PERIPH_ID_MIPI,
  92. PERIPH_ID_HDMI,
  93. PERIPH_ID_CSI,
  94. PERIPH_ID_TVDAC,
  95. PERIPH_ID_I2C2,
  96. PERIPH_ID_UART3,
  97. /* 56 */
  98. PERIPH_ID_RESERVED56,
  99. PERIPH_ID_EMC,
  100. PERIPH_ID_USB2,
  101. PERIPH_ID_USB3,
  102. PERIPH_ID_MPE,
  103. PERIPH_ID_VDE,
  104. PERIPH_ID_BSEA,
  105. PERIPH_ID_BSEV,
  106. /* Upper word 95:64 */
  107. PERIPH_ID_SPEEDO,
  108. PERIPH_ID_UART4,
  109. PERIPH_ID_UART5,
  110. PERIPH_ID_I2C3,
  111. PERIPH_ID_SBC4,
  112. PERIPH_ID_SDMMC3,
  113. PERIPH_ID_PCIE,
  114. PERIPH_ID_OWR,
  115. /* 72 */
  116. PERIPH_ID_AFI,
  117. PERIPH_ID_CORESIGHT,
  118. PERIPH_ID_PCIEXCLK,
  119. PERIPH_ID_AVPUCQ,
  120. PERIPH_ID_RESERVED76,
  121. PERIPH_ID_RESERVED77,
  122. PERIPH_ID_RESERVED78,
  123. PERIPH_ID_RESERVED79,
  124. /* 80 */
  125. PERIPH_ID_RESERVED80,
  126. PERIPH_ID_RESERVED81,
  127. PERIPH_ID_RESERVED82,
  128. PERIPH_ID_RESERVED83,
  129. PERIPH_ID_IRAMA,
  130. PERIPH_ID_IRAMB,
  131. PERIPH_ID_IRAMC,
  132. PERIPH_ID_IRAMD,
  133. /* 88 */
  134. PERIPH_ID_CRAM2,
  135. PERIPH_ID_SYNC_CLK_DOUBLER,
  136. PERIPH_ID_CLK_M_DOUBLER,
  137. PERIPH_ID_RESERVED91,
  138. PERIPH_ID_SUS_OUT,
  139. PERIPH_ID_DEV2_OUT,
  140. PERIPH_ID_DEV1_OUT,
  141. PERIPH_ID_COUNT,
  142. PERIPH_ID_NONE = -1,
  143. };
  144. enum pll_out_id {
  145. PLL_OUT1,
  146. PLL_OUT2,
  147. PLL_OUT3,
  148. PLL_OUT4
  149. };
  150. /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
  151. #define PERIPH_REG(id) ((id) >> 5)
  152. /* Mask value for a clock (within PERIPH_REG(id)) */
  153. #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
  154. /* return 1 if a PLL ID is in range, and not a simple PLL */
  155. #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
  156. (id) < CLOCK_ID_FIRST_SIMPLE)
  157. /* return 1 if a peripheral ID is in range */
  158. #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
  159. (id) < PERIPH_ID_COUNT)
  160. #endif /* _CLOCK_TABLES_H_ */