bd82x6x.c 2.2 KB

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  1. /*
  2. * Copyright (C) 2014 Google, Inc
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <fdtdec.h>
  10. #include <malloc.h>
  11. #include <pch.h>
  12. #include <asm/lapic.h>
  13. #include <asm/pci.h>
  14. #include <asm/arch/bd82x6x.h>
  15. #include <asm/arch/model_206ax.h>
  16. #include <asm/arch/pch.h>
  17. #include <asm/arch/sandybridge.h>
  18. #define BIOS_CTRL 0xdc
  19. static int bd82x6x_probe(struct udevice *dev)
  20. {
  21. const void *blob = gd->fdt_blob;
  22. int gma_node;
  23. int ret;
  24. if (!(gd->flags & GD_FLG_RELOC))
  25. return 0;
  26. /* Cause the SATA device to do its init */
  27. uclass_first_device(UCLASS_DISK, &dev);
  28. bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
  29. bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
  30. gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA);
  31. if (gma_node < 0) {
  32. debug("%s: Cannot find GMA node\n", __func__);
  33. return -EINVAL;
  34. }
  35. ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev);
  36. if (ret)
  37. return ret;
  38. ret = gma_func0_init(dev, blob, gma_node);
  39. if (ret)
  40. return ret;
  41. return 0;
  42. }
  43. static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
  44. {
  45. u32 rcba;
  46. dm_pci_read_config32(dev, PCH_RCBA, &rcba);
  47. /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
  48. rcba = rcba & 0xffffc000;
  49. *sbasep = rcba + 0x3800;
  50. return 0;
  51. }
  52. static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
  53. {
  54. return PCHV_9;
  55. }
  56. static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
  57. {
  58. uint8_t bios_cntl;
  59. /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
  60. dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
  61. if (protect) {
  62. bios_cntl &= ~BIOS_CTRL_BIOSWE;
  63. bios_cntl |= BIT(5);
  64. } else {
  65. bios_cntl |= BIOS_CTRL_BIOSWE;
  66. bios_cntl &= ~BIT(5);
  67. }
  68. dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
  69. return 0;
  70. }
  71. static const struct pch_ops bd82x6x_pch_ops = {
  72. .get_sbase = bd82x6x_pch_get_sbase,
  73. .get_version = bd82x6x_pch_get_version,
  74. .set_spi_protect = bd82x6x_set_spi_protect,
  75. };
  76. static const struct udevice_id bd82x6x_ids[] = {
  77. { .compatible = "intel,bd82x6x" },
  78. { }
  79. };
  80. U_BOOT_DRIVER(bd82x6x_drv) = {
  81. .name = "bd82x6x",
  82. .id = UCLASS_PCH,
  83. .of_match = bd82x6x_ids,
  84. .probe = bd82x6x_probe,
  85. .ops = &bd82x6x_pch_ops,
  86. };