fsl_secure_boot.h 3.2 KB

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  1. /*
  2. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __FSL_SECURE_BOOT_H
  7. #define __FSL_SECURE_BOOT_H
  8. #include <asm/config_mpc85xx.h>
  9. #ifdef CONFIG_SECURE_BOOT
  10. #ifndef CONFIG_FIT_SIGNATURE
  11. #define CONFIG_CHAIN_OF_TRUST
  12. #endif
  13. #if defined(CONFIG_FSL_CORENET)
  14. #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
  15. #elif defined(CONFIG_BSC9132QDS)
  16. #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
  17. #elif defined(CONFIG_C29XPCIE)
  18. #define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
  19. #else
  20. #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
  21. #endif
  22. #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
  23. #if defined(CONFIG_B4860QDS) || \
  24. defined(CONFIG_T4240QDS) || \
  25. defined(CONFIG_T2080QDS) || \
  26. defined(CONFIG_T2080RDB) || \
  27. defined(CONFIG_T1040QDS) || \
  28. defined(CONFIG_T104xD4QDS) || \
  29. defined(CONFIG_T104xRDB) || \
  30. defined(CONFIG_T104xD4RDB) || \
  31. defined(CONFIG_PPC_T1023) || \
  32. defined(CONFIG_PPC_T1024)
  33. #define CONFIG_SYS_CPC_REINIT_F
  34. #define CONFIG_KEY_REVOCATION
  35. #undef CONFIG_SYS_INIT_L3_ADDR
  36. #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
  37. #endif
  38. #if defined(CONFIG_RAMBOOT_PBL)
  39. #undef CONFIG_SYS_INIT_L3_ADDR
  40. #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
  41. #endif
  42. #if defined(CONFIG_C29XPCIE)
  43. #define CONFIG_KEY_REVOCATION
  44. #endif
  45. #if defined(CONFIG_PPC_P3041) || \
  46. defined(CONFIG_PPC_P4080) || \
  47. defined(CONFIG_PPC_P5020) || \
  48. defined(CONFIG_PPC_P5040) || \
  49. defined(CONFIG_PPC_P2041)
  50. #define CONFIG_FSL_TRUST_ARCH_v1
  51. #endif
  52. #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
  53. /* The key used for verification of next level images
  54. * is picked up from an Extension Table which has
  55. * been verified by the ISBC (Internal Secure boot Code)
  56. * in boot ROM of the SoC.
  57. * The feature is only applicable in case of NOR boot and is
  58. * not applicable in case of RAMBOOT (NAND, SD, SPI).
  59. */
  60. #define CONFIG_FSL_ISBC_KEY_EXT
  61. #endif
  62. #endif /* #ifdef CONFIG_SECURE_BOOT */
  63. #ifdef CONFIG_CHAIN_OF_TRUST
  64. #define CONFIG_CMD_ESBC_VALIDATE
  65. #define CONFIG_CMD_BLOB
  66. #define CONFIG_FSL_SEC_MON
  67. #define CONFIG_SHA_PROG_HW_ACCEL
  68. #define CONFIG_RSA
  69. #define CONFIG_RSA_FREESCALE_EXP
  70. #ifndef CONFIG_DM
  71. #define CONFIG_DM
  72. #endif
  73. #ifndef CONFIG_FSL_CAAM
  74. #define CONFIG_FSL_CAAM
  75. #endif
  76. /* If Boot Script is not on NOR and is required to be copied on RAM */
  77. #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
  78. #define CONFIG_BS_HDR_ADDR_RAM 0x00010000
  79. #define CONFIG_BS_HDR_ADDR_FLASH 0x00800000
  80. #define CONFIG_BS_HDR_SIZE 0x00002000
  81. #define CONFIG_BS_ADDR_RAM 0x00012000
  82. #define CONFIG_BS_ADDR_FLASH 0x00802000
  83. #define CONFIG_BS_SIZE 0x00001000
  84. #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
  85. #else
  86. /* The bootscript header address is different for B4860 because the NOR
  87. * mapping is different on B4 due to reduced NOR size.
  88. */
  89. #if defined(CONFIG_B4860QDS)
  90. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
  91. #elif defined(CONFIG_FSL_CORENET)
  92. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
  93. #elif defined(CONFIG_BSC9132QDS)
  94. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
  95. #elif defined(CONFIG_C29XPCIE)
  96. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
  97. #else
  98. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
  99. #endif
  100. #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
  101. #include <config_fsl_chain_trust.h>
  102. #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
  103. #endif