ehci-hcd.c 46 KB

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  1. /*-
  2. * Copyright (c) 2007-2008, Juniper Networks, Inc.
  3. * Copyright (c) 2008, Excito Elektronik i Skåne AB
  4. * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
  5. *
  6. * All rights reserved.
  7. *
  8. * SPDX-License-Identifier: GPL-2.0
  9. */
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <asm/byteorder.h>
  14. #include <asm/unaligned.h>
  15. #include <usb.h>
  16. #include <asm/io.h>
  17. #include <malloc.h>
  18. #include <memalign.h>
  19. #include <watchdog.h>
  20. #include <linux/compiler.h>
  21. #include "ehci.h"
  22. #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  23. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  24. #endif
  25. /*
  26. * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
  27. * Let's time out after 8 to have a little safety margin on top of that.
  28. */
  29. #define HCHALT_TIMEOUT (8 * 1000)
  30. #ifndef CONFIG_DM_USB
  31. static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
  32. #endif
  33. #define ALIGN_END_ADDR(type, ptr, size) \
  34. ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
  35. static struct descriptor {
  36. struct usb_hub_descriptor hub;
  37. struct usb_device_descriptor device;
  38. struct usb_linux_config_descriptor config;
  39. struct usb_linux_interface_descriptor interface;
  40. struct usb_endpoint_descriptor endpoint;
  41. } __attribute__ ((packed)) descriptor = {
  42. {
  43. 0x8, /* bDescLength */
  44. 0x29, /* bDescriptorType: hub descriptor */
  45. 2, /* bNrPorts -- runtime modified */
  46. 0, /* wHubCharacteristics */
  47. 10, /* bPwrOn2PwrGood */
  48. 0, /* bHubCntrCurrent */
  49. {}, /* Device removable */
  50. {} /* at most 7 ports! XXX */
  51. },
  52. {
  53. 0x12, /* bLength */
  54. 1, /* bDescriptorType: UDESC_DEVICE */
  55. cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
  56. 9, /* bDeviceClass: UDCLASS_HUB */
  57. 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
  58. 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
  59. 64, /* bMaxPacketSize: 64 bytes */
  60. 0x0000, /* idVendor */
  61. 0x0000, /* idProduct */
  62. cpu_to_le16(0x0100), /* bcdDevice */
  63. 1, /* iManufacturer */
  64. 2, /* iProduct */
  65. 0, /* iSerialNumber */
  66. 1 /* bNumConfigurations: 1 */
  67. },
  68. {
  69. 0x9,
  70. 2, /* bDescriptorType: UDESC_CONFIG */
  71. cpu_to_le16(0x19),
  72. 1, /* bNumInterface */
  73. 1, /* bConfigurationValue */
  74. 0, /* iConfiguration */
  75. 0x40, /* bmAttributes: UC_SELF_POWER */
  76. 0 /* bMaxPower */
  77. },
  78. {
  79. 0x9, /* bLength */
  80. 4, /* bDescriptorType: UDESC_INTERFACE */
  81. 0, /* bInterfaceNumber */
  82. 0, /* bAlternateSetting */
  83. 1, /* bNumEndpoints */
  84. 9, /* bInterfaceClass: UICLASS_HUB */
  85. 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
  86. 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  87. 0 /* iInterface */
  88. },
  89. {
  90. 0x7, /* bLength */
  91. 5, /* bDescriptorType: UDESC_ENDPOINT */
  92. 0x81, /* bEndpointAddress:
  93. * UE_DIR_IN | EHCI_INTR_ENDPT
  94. */
  95. 3, /* bmAttributes: UE_INTERRUPT */
  96. 8, /* wMaxPacketSize */
  97. 255 /* bInterval */
  98. },
  99. };
  100. #if defined(CONFIG_EHCI_IS_TDI)
  101. #define ehci_is_TDI() (1)
  102. #else
  103. #define ehci_is_TDI() (0)
  104. #endif
  105. static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
  106. {
  107. #ifdef CONFIG_DM_USB
  108. return dev_get_priv(usb_get_bus(udev->dev));
  109. #else
  110. return udev->controller;
  111. #endif
  112. }
  113. static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
  114. {
  115. return PORTSC_PSPD(reg);
  116. }
  117. static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
  118. {
  119. uint32_t tmp;
  120. uint32_t *reg_ptr;
  121. reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
  122. tmp = ehci_readl(reg_ptr);
  123. tmp |= USBMODE_CM_HC;
  124. #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
  125. tmp |= USBMODE_BE;
  126. #endif
  127. ehci_writel(reg_ptr, tmp);
  128. }
  129. static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
  130. uint32_t *reg)
  131. {
  132. mdelay(50);
  133. }
  134. static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
  135. {
  136. if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
  137. /* Printing the message would cause a scan failure! */
  138. debug("The request port(%u) is not configured\n", port);
  139. return NULL;
  140. }
  141. return (uint32_t *)&ctrl->hcor->or_portsc[port];
  142. }
  143. static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
  144. {
  145. uint32_t result;
  146. do {
  147. result = ehci_readl(ptr);
  148. udelay(5);
  149. if (result == ~(uint32_t)0)
  150. return -1;
  151. result &= mask;
  152. if (result == done)
  153. return 0;
  154. usec--;
  155. } while (usec > 0);
  156. return -1;
  157. }
  158. static int ehci_reset(struct ehci_ctrl *ctrl)
  159. {
  160. uint32_t cmd;
  161. int ret = 0;
  162. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  163. cmd = (cmd & ~CMD_RUN) | CMD_RESET;
  164. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  165. ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
  166. CMD_RESET, 0, 250 * 1000);
  167. if (ret < 0) {
  168. printf("EHCI fail to reset\n");
  169. goto out;
  170. }
  171. if (ehci_is_TDI())
  172. ctrl->ops.set_usb_mode(ctrl);
  173. #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
  174. cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
  175. cmd &= ~TXFIFO_THRESH_MASK;
  176. cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
  177. ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
  178. #endif
  179. out:
  180. return ret;
  181. }
  182. static int ehci_shutdown(struct ehci_ctrl *ctrl)
  183. {
  184. int i, ret = 0;
  185. uint32_t cmd, reg;
  186. if (!ctrl || !ctrl->hcor)
  187. return -EINVAL;
  188. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  189. cmd &= ~(CMD_PSE | CMD_ASE);
  190. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  191. ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
  192. 100 * 1000);
  193. if (!ret) {
  194. for (i = 0; i < CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS; i++) {
  195. reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
  196. reg |= EHCI_PS_SUSP;
  197. ehci_writel(&ctrl->hcor->or_portsc[i], reg);
  198. }
  199. cmd &= ~CMD_RUN;
  200. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  201. ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
  202. HCHALT_TIMEOUT);
  203. }
  204. if (ret)
  205. puts("EHCI failed to shut down host controller.\n");
  206. return ret;
  207. }
  208. static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
  209. {
  210. uint32_t delta, next;
  211. uint32_t addr = (unsigned long)buf;
  212. int idx;
  213. if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
  214. debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
  215. flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
  216. idx = 0;
  217. while (idx < QT_BUFFER_CNT) {
  218. td->qt_buffer[idx] = cpu_to_hc32(addr);
  219. td->qt_buffer_hi[idx] = 0;
  220. next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
  221. delta = next - addr;
  222. if (delta >= sz)
  223. break;
  224. sz -= delta;
  225. addr = next;
  226. idx++;
  227. }
  228. if (idx == QT_BUFFER_CNT) {
  229. printf("out of buffer pointers (%zu bytes left)\n", sz);
  230. return -1;
  231. }
  232. return 0;
  233. }
  234. static inline u8 ehci_encode_speed(enum usb_device_speed speed)
  235. {
  236. #define QH_HIGH_SPEED 2
  237. #define QH_FULL_SPEED 0
  238. #define QH_LOW_SPEED 1
  239. if (speed == USB_SPEED_HIGH)
  240. return QH_HIGH_SPEED;
  241. if (speed == USB_SPEED_LOW)
  242. return QH_LOW_SPEED;
  243. return QH_FULL_SPEED;
  244. }
  245. static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
  246. struct QH *qh)
  247. {
  248. struct usb_device *ttdev;
  249. int parent_devnum;
  250. if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
  251. return;
  252. /*
  253. * For full / low speed devices we need to get the devnum and portnr of
  254. * the tt, so of the first upstream usb-2 hub, there may be usb-1 hubs
  255. * in the tree before that one!
  256. */
  257. #ifdef CONFIG_DM_USB
  258. /*
  259. * When called from usb-uclass.c: usb_scan_device() udev->dev points
  260. * to the parent udevice, not the actual udevice belonging to the
  261. * udev as the device is not instantiated yet. So when searching
  262. * for the first usb-2 parent start with udev->dev not
  263. * udev->dev->parent .
  264. */
  265. struct udevice *parent;
  266. struct usb_device *uparent;
  267. ttdev = udev;
  268. parent = udev->dev;
  269. uparent = dev_get_parent_priv(parent);
  270. while (uparent->speed != USB_SPEED_HIGH) {
  271. struct udevice *dev = parent;
  272. if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) {
  273. printf("ehci: Error cannot find high-speed parent of usb-1 device\n");
  274. return;
  275. }
  276. ttdev = dev_get_parent_priv(dev);
  277. parent = dev->parent;
  278. uparent = dev_get_parent_priv(parent);
  279. }
  280. parent_devnum = uparent->devnum;
  281. #else
  282. ttdev = udev;
  283. while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH)
  284. ttdev = ttdev->parent;
  285. if (!ttdev->parent)
  286. return;
  287. parent_devnum = ttdev->parent->devnum;
  288. #endif
  289. qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(ttdev->portnr) |
  290. QH_ENDPT2_HUBADDR(parent_devnum));
  291. }
  292. static int
  293. ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
  294. int length, struct devrequest *req)
  295. {
  296. ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
  297. struct qTD *qtd;
  298. int qtd_count = 0;
  299. int qtd_counter = 0;
  300. volatile struct qTD *vtd;
  301. unsigned long ts;
  302. uint32_t *tdp;
  303. uint32_t endpt, maxpacket, token, usbsts;
  304. uint32_t c, toggle;
  305. uint32_t cmd;
  306. int timeout;
  307. int ret = 0;
  308. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  309. debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
  310. buffer, length, req);
  311. if (req != NULL)
  312. debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
  313. req->request, req->request,
  314. req->requesttype, req->requesttype,
  315. le16_to_cpu(req->value), le16_to_cpu(req->value),
  316. le16_to_cpu(req->index));
  317. #define PKT_ALIGN 512
  318. /*
  319. * The USB transfer is split into qTD transfers. Eeach qTD transfer is
  320. * described by a transfer descriptor (the qTD). The qTDs form a linked
  321. * list with a queue head (QH).
  322. *
  323. * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
  324. * have its beginning in a qTD transfer and its end in the following
  325. * one, so the qTD transfer lengths have to be chosen accordingly.
  326. *
  327. * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
  328. * single pages. The first data buffer can start at any offset within a
  329. * page (not considering the cache-line alignment issues), while the
  330. * following buffers must be page-aligned. There is no alignment
  331. * constraint on the size of a qTD transfer.
  332. */
  333. if (req != NULL)
  334. /* 1 qTD will be needed for SETUP, and 1 for ACK. */
  335. qtd_count += 1 + 1;
  336. if (length > 0 || req == NULL) {
  337. /*
  338. * Determine the qTD transfer size that will be used for the
  339. * data payload (not considering the first qTD transfer, which
  340. * may be longer or shorter, and the final one, which may be
  341. * shorter).
  342. *
  343. * In order to keep each packet within a qTD transfer, the qTD
  344. * transfer size is aligned to PKT_ALIGN, which is a multiple of
  345. * wMaxPacketSize (except in some cases for interrupt transfers,
  346. * see comment in submit_int_msg()).
  347. *
  348. * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
  349. * QT_BUFFER_CNT full pages will be used.
  350. */
  351. int xfr_sz = QT_BUFFER_CNT;
  352. /*
  353. * However, if the input buffer is not aligned to PKT_ALIGN, the
  354. * qTD transfer size will be one page shorter, and the first qTD
  355. * data buffer of each transfer will be page-unaligned.
  356. */
  357. if ((unsigned long)buffer & (PKT_ALIGN - 1))
  358. xfr_sz--;
  359. /* Convert the qTD transfer size to bytes. */
  360. xfr_sz *= EHCI_PAGE_SIZE;
  361. /*
  362. * Approximate by excess the number of qTDs that will be
  363. * required for the data payload. The exact formula is way more
  364. * complicated and saves at most 2 qTDs, i.e. a total of 128
  365. * bytes.
  366. */
  367. qtd_count += 2 + length / xfr_sz;
  368. }
  369. /*
  370. * Threshold value based on the worst-case total size of the allocated qTDs for
  371. * a mass-storage transfer of 65535 blocks of 512 bytes.
  372. */
  373. #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
  374. #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
  375. #endif
  376. qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
  377. if (qtd == NULL) {
  378. printf("unable to allocate TDs\n");
  379. return -1;
  380. }
  381. memset(qh, 0, sizeof(struct QH));
  382. memset(qtd, 0, qtd_count * sizeof(*qtd));
  383. toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
  384. /*
  385. * Setup QH (3.6 in ehci-r10.pdf)
  386. *
  387. * qh_link ................. 03-00 H
  388. * qh_endpt1 ............... 07-04 H
  389. * qh_endpt2 ............... 0B-08 H
  390. * - qh_curtd
  391. * qh_overlay.qt_next ...... 13-10 H
  392. * - qh_overlay.qt_altnext
  393. */
  394. qh->qh_link = cpu_to_hc32((unsigned long)&ctrl->qh_list | QH_LINK_TYPE_QH);
  395. c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
  396. maxpacket = usb_maxpacket(dev, pipe);
  397. endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
  398. QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
  399. QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
  400. QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
  401. QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
  402. QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
  403. qh->qh_endpt1 = cpu_to_hc32(endpt);
  404. endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
  405. qh->qh_endpt2 = cpu_to_hc32(endpt);
  406. ehci_update_endpt2_dev_n_port(dev, qh);
  407. qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  408. qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  409. tdp = &qh->qh_overlay.qt_next;
  410. if (req != NULL) {
  411. /*
  412. * Setup request qTD (3.5 in ehci-r10.pdf)
  413. *
  414. * qt_next ................ 03-00 H
  415. * qt_altnext ............. 07-04 H
  416. * qt_token ............... 0B-08 H
  417. *
  418. * [ buffer, buffer_hi ] loaded with "req".
  419. */
  420. qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  421. qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  422. token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
  423. QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
  424. QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
  425. QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
  426. qtd[qtd_counter].qt_token = cpu_to_hc32(token);
  427. if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
  428. printf("unable to construct SETUP TD\n");
  429. goto fail;
  430. }
  431. /* Update previous qTD! */
  432. *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
  433. tdp = &qtd[qtd_counter++].qt_next;
  434. toggle = 1;
  435. }
  436. if (length > 0 || req == NULL) {
  437. uint8_t *buf_ptr = buffer;
  438. int left_length = length;
  439. do {
  440. /*
  441. * Determine the size of this qTD transfer. By default,
  442. * QT_BUFFER_CNT full pages can be used.
  443. */
  444. int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
  445. /*
  446. * However, if the input buffer is not page-aligned, the
  447. * portion of the first page before the buffer start
  448. * offset within that page is unusable.
  449. */
  450. xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
  451. /*
  452. * In order to keep each packet within a qTD transfer,
  453. * align the qTD transfer size to PKT_ALIGN.
  454. */
  455. xfr_bytes &= ~(PKT_ALIGN - 1);
  456. /*
  457. * This transfer may be shorter than the available qTD
  458. * transfer size that has just been computed.
  459. */
  460. xfr_bytes = min(xfr_bytes, left_length);
  461. /*
  462. * Setup request qTD (3.5 in ehci-r10.pdf)
  463. *
  464. * qt_next ................ 03-00 H
  465. * qt_altnext ............. 07-04 H
  466. * qt_token ............... 0B-08 H
  467. *
  468. * [ buffer, buffer_hi ] loaded with "buffer".
  469. */
  470. qtd[qtd_counter].qt_next =
  471. cpu_to_hc32(QT_NEXT_TERMINATE);
  472. qtd[qtd_counter].qt_altnext =
  473. cpu_to_hc32(QT_NEXT_TERMINATE);
  474. token = QT_TOKEN_DT(toggle) |
  475. QT_TOKEN_TOTALBYTES(xfr_bytes) |
  476. QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
  477. QT_TOKEN_CERR(3) |
  478. QT_TOKEN_PID(usb_pipein(pipe) ?
  479. QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
  480. QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
  481. qtd[qtd_counter].qt_token = cpu_to_hc32(token);
  482. if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
  483. xfr_bytes)) {
  484. printf("unable to construct DATA TD\n");
  485. goto fail;
  486. }
  487. /* Update previous qTD! */
  488. *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
  489. tdp = &qtd[qtd_counter++].qt_next;
  490. /*
  491. * Data toggle has to be adjusted since the qTD transfer
  492. * size is not always an even multiple of
  493. * wMaxPacketSize.
  494. */
  495. if ((xfr_bytes / maxpacket) & 1)
  496. toggle ^= 1;
  497. buf_ptr += xfr_bytes;
  498. left_length -= xfr_bytes;
  499. } while (left_length > 0);
  500. }
  501. if (req != NULL) {
  502. /*
  503. * Setup request qTD (3.5 in ehci-r10.pdf)
  504. *
  505. * qt_next ................ 03-00 H
  506. * qt_altnext ............. 07-04 H
  507. * qt_token ............... 0B-08 H
  508. */
  509. qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  510. qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  511. token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
  512. QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
  513. QT_TOKEN_PID(usb_pipein(pipe) ?
  514. QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
  515. QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
  516. qtd[qtd_counter].qt_token = cpu_to_hc32(token);
  517. /* Update previous qTD! */
  518. *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
  519. tdp = &qtd[qtd_counter++].qt_next;
  520. }
  521. ctrl->qh_list.qh_link = cpu_to_hc32((unsigned long)qh | QH_LINK_TYPE_QH);
  522. /* Flush dcache */
  523. flush_dcache_range((unsigned long)&ctrl->qh_list,
  524. ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
  525. flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
  526. flush_dcache_range((unsigned long)qtd,
  527. ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
  528. /* Set async. queue head pointer. */
  529. ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)&ctrl->qh_list);
  530. usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
  531. ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
  532. /* Enable async. schedule. */
  533. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  534. cmd |= CMD_ASE;
  535. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  536. ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
  537. 100 * 1000);
  538. if (ret < 0) {
  539. printf("EHCI fail timeout STS_ASS set\n");
  540. goto fail;
  541. }
  542. /* Wait for TDs to be processed. */
  543. ts = get_timer(0);
  544. vtd = &qtd[qtd_counter - 1];
  545. timeout = USB_TIMEOUT_MS(pipe);
  546. do {
  547. /* Invalidate dcache */
  548. invalidate_dcache_range((unsigned long)&ctrl->qh_list,
  549. ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
  550. invalidate_dcache_range((unsigned long)qh,
  551. ALIGN_END_ADDR(struct QH, qh, 1));
  552. invalidate_dcache_range((unsigned long)qtd,
  553. ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
  554. token = hc32_to_cpu(vtd->qt_token);
  555. if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
  556. break;
  557. WATCHDOG_RESET();
  558. } while (get_timer(ts) < timeout);
  559. /*
  560. * Invalidate the memory area occupied by buffer
  561. * Don't try to fix the buffer alignment, if it isn't properly
  562. * aligned it's upper layer's fault so let invalidate_dcache_range()
  563. * vow about it. But we have to fix the length as it's actual
  564. * transfer length and can be unaligned. This is potentially
  565. * dangerous operation, it's responsibility of the calling
  566. * code to make sure enough space is reserved.
  567. */
  568. invalidate_dcache_range((unsigned long)buffer,
  569. ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
  570. /* Check that the TD processing happened */
  571. if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
  572. printf("EHCI timed out on TD - token=%#x\n", token);
  573. /* Disable async schedule. */
  574. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  575. cmd &= ~CMD_ASE;
  576. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  577. ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
  578. 100 * 1000);
  579. if (ret < 0) {
  580. printf("EHCI fail timeout STS_ASS reset\n");
  581. goto fail;
  582. }
  583. token = hc32_to_cpu(qh->qh_overlay.qt_token);
  584. if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
  585. debug("TOKEN=%#x\n", token);
  586. switch (QT_TOKEN_GET_STATUS(token) &
  587. ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
  588. case 0:
  589. toggle = QT_TOKEN_GET_DT(token);
  590. usb_settoggle(dev, usb_pipeendpoint(pipe),
  591. usb_pipeout(pipe), toggle);
  592. dev->status = 0;
  593. break;
  594. case QT_TOKEN_STATUS_HALTED:
  595. dev->status = USB_ST_STALLED;
  596. break;
  597. case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
  598. case QT_TOKEN_STATUS_DATBUFERR:
  599. dev->status = USB_ST_BUF_ERR;
  600. break;
  601. case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
  602. case QT_TOKEN_STATUS_BABBLEDET:
  603. dev->status = USB_ST_BABBLE_DET;
  604. break;
  605. default:
  606. dev->status = USB_ST_CRC_ERR;
  607. if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
  608. dev->status |= USB_ST_STALLED;
  609. break;
  610. }
  611. dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
  612. } else {
  613. dev->act_len = 0;
  614. #ifndef CONFIG_USB_EHCI_FARADAY
  615. debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
  616. dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
  617. ehci_readl(&ctrl->hcor->or_portsc[0]),
  618. ehci_readl(&ctrl->hcor->or_portsc[1]));
  619. #endif
  620. }
  621. free(qtd);
  622. return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
  623. fail:
  624. free(qtd);
  625. return -1;
  626. }
  627. static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
  628. void *buffer, int length, struct devrequest *req)
  629. {
  630. uint8_t tmpbuf[4];
  631. u16 typeReq;
  632. void *srcptr = NULL;
  633. int len, srclen;
  634. uint32_t reg;
  635. uint32_t *status_reg;
  636. int port = le16_to_cpu(req->index) & 0xff;
  637. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  638. srclen = 0;
  639. debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
  640. req->request, req->request,
  641. req->requesttype, req->requesttype,
  642. le16_to_cpu(req->value), le16_to_cpu(req->index));
  643. typeReq = req->request | req->requesttype << 8;
  644. switch (typeReq) {
  645. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  646. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  647. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  648. status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
  649. if (!status_reg)
  650. return -1;
  651. break;
  652. default:
  653. status_reg = NULL;
  654. break;
  655. }
  656. switch (typeReq) {
  657. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  658. switch (le16_to_cpu(req->value) >> 8) {
  659. case USB_DT_DEVICE:
  660. debug("USB_DT_DEVICE request\n");
  661. srcptr = &descriptor.device;
  662. srclen = descriptor.device.bLength;
  663. break;
  664. case USB_DT_CONFIG:
  665. debug("USB_DT_CONFIG config\n");
  666. srcptr = &descriptor.config;
  667. srclen = descriptor.config.bLength +
  668. descriptor.interface.bLength +
  669. descriptor.endpoint.bLength;
  670. break;
  671. case USB_DT_STRING:
  672. debug("USB_DT_STRING config\n");
  673. switch (le16_to_cpu(req->value) & 0xff) {
  674. case 0: /* Language */
  675. srcptr = "\4\3\1\0";
  676. srclen = 4;
  677. break;
  678. case 1: /* Vendor */
  679. srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
  680. srclen = 14;
  681. break;
  682. case 2: /* Product */
  683. srcptr = "\52\3E\0H\0C\0I\0 "
  684. "\0H\0o\0s\0t\0 "
  685. "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
  686. srclen = 42;
  687. break;
  688. default:
  689. debug("unknown value DT_STRING %x\n",
  690. le16_to_cpu(req->value));
  691. goto unknown;
  692. }
  693. break;
  694. default:
  695. debug("unknown value %x\n", le16_to_cpu(req->value));
  696. goto unknown;
  697. }
  698. break;
  699. case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
  700. switch (le16_to_cpu(req->value) >> 8) {
  701. case USB_DT_HUB:
  702. debug("USB_DT_HUB config\n");
  703. srcptr = &descriptor.hub;
  704. srclen = descriptor.hub.bLength;
  705. break;
  706. default:
  707. debug("unknown value %x\n", le16_to_cpu(req->value));
  708. goto unknown;
  709. }
  710. break;
  711. case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
  712. debug("USB_REQ_SET_ADDRESS\n");
  713. ctrl->rootdev = le16_to_cpu(req->value);
  714. break;
  715. case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
  716. debug("USB_REQ_SET_CONFIGURATION\n");
  717. /* Nothing to do */
  718. break;
  719. case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
  720. tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
  721. tmpbuf[1] = 0;
  722. srcptr = tmpbuf;
  723. srclen = 2;
  724. break;
  725. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  726. memset(tmpbuf, 0, 4);
  727. reg = ehci_readl(status_reg);
  728. if (reg & EHCI_PS_CS)
  729. tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
  730. if (reg & EHCI_PS_PE)
  731. tmpbuf[0] |= USB_PORT_STAT_ENABLE;
  732. if (reg & EHCI_PS_SUSP)
  733. tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
  734. if (reg & EHCI_PS_OCA)
  735. tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
  736. if (reg & EHCI_PS_PR)
  737. tmpbuf[0] |= USB_PORT_STAT_RESET;
  738. if (reg & EHCI_PS_PP)
  739. tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
  740. if (ehci_is_TDI()) {
  741. switch (ctrl->ops.get_port_speed(ctrl, reg)) {
  742. case PORTSC_PSPD_FS:
  743. break;
  744. case PORTSC_PSPD_LS:
  745. tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
  746. break;
  747. case PORTSC_PSPD_HS:
  748. default:
  749. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  750. break;
  751. }
  752. } else {
  753. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  754. }
  755. if (reg & EHCI_PS_CSC)
  756. tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
  757. if (reg & EHCI_PS_PEC)
  758. tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
  759. if (reg & EHCI_PS_OCC)
  760. tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
  761. if (ctrl->portreset & (1 << port))
  762. tmpbuf[2] |= USB_PORT_STAT_C_RESET;
  763. srcptr = tmpbuf;
  764. srclen = 4;
  765. break;
  766. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  767. reg = ehci_readl(status_reg);
  768. reg &= ~EHCI_PS_CLEAR;
  769. switch (le16_to_cpu(req->value)) {
  770. case USB_PORT_FEAT_ENABLE:
  771. reg |= EHCI_PS_PE;
  772. ehci_writel(status_reg, reg);
  773. break;
  774. case USB_PORT_FEAT_POWER:
  775. if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
  776. reg |= EHCI_PS_PP;
  777. ehci_writel(status_reg, reg);
  778. }
  779. break;
  780. case USB_PORT_FEAT_RESET:
  781. if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
  782. !ehci_is_TDI() &&
  783. EHCI_PS_IS_LOWSPEED(reg)) {
  784. /* Low speed device, give up ownership. */
  785. debug("port %d low speed --> companion\n",
  786. port - 1);
  787. reg |= EHCI_PS_PO;
  788. ehci_writel(status_reg, reg);
  789. return -ENXIO;
  790. } else {
  791. int ret;
  792. reg |= EHCI_PS_PR;
  793. reg &= ~EHCI_PS_PE;
  794. ehci_writel(status_reg, reg);
  795. /*
  796. * caller must wait, then call GetPortStatus
  797. * usb 2.0 specification say 50 ms resets on
  798. * root
  799. */
  800. ctrl->ops.powerup_fixup(ctrl, status_reg, &reg);
  801. ehci_writel(status_reg, reg & ~EHCI_PS_PR);
  802. /*
  803. * A host controller must terminate the reset
  804. * and stabilize the state of the port within
  805. * 2 milliseconds
  806. */
  807. ret = handshake(status_reg, EHCI_PS_PR, 0,
  808. 2 * 1000);
  809. if (!ret) {
  810. reg = ehci_readl(status_reg);
  811. if ((reg & (EHCI_PS_PE | EHCI_PS_CS))
  812. == EHCI_PS_CS && !ehci_is_TDI()) {
  813. debug("port %d full speed --> companion\n", port - 1);
  814. reg &= ~EHCI_PS_CLEAR;
  815. reg |= EHCI_PS_PO;
  816. ehci_writel(status_reg, reg);
  817. return -ENXIO;
  818. } else {
  819. ctrl->portreset |= 1 << port;
  820. }
  821. } else {
  822. printf("port(%d) reset error\n",
  823. port - 1);
  824. }
  825. }
  826. break;
  827. case USB_PORT_FEAT_TEST:
  828. ehci_shutdown(ctrl);
  829. reg &= ~(0xf << 16);
  830. reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
  831. ehci_writel(status_reg, reg);
  832. break;
  833. default:
  834. debug("unknown feature %x\n", le16_to_cpu(req->value));
  835. goto unknown;
  836. }
  837. /* unblock posted writes */
  838. (void) ehci_readl(&ctrl->hcor->or_usbcmd);
  839. break;
  840. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  841. reg = ehci_readl(status_reg);
  842. reg &= ~EHCI_PS_CLEAR;
  843. switch (le16_to_cpu(req->value)) {
  844. case USB_PORT_FEAT_ENABLE:
  845. reg &= ~EHCI_PS_PE;
  846. break;
  847. case USB_PORT_FEAT_C_ENABLE:
  848. reg |= EHCI_PS_PE;
  849. break;
  850. case USB_PORT_FEAT_POWER:
  851. if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
  852. reg &= ~EHCI_PS_PP;
  853. break;
  854. case USB_PORT_FEAT_C_CONNECTION:
  855. reg |= EHCI_PS_CSC;
  856. break;
  857. case USB_PORT_FEAT_OVER_CURRENT:
  858. reg |= EHCI_PS_OCC;
  859. break;
  860. case USB_PORT_FEAT_C_RESET:
  861. ctrl->portreset &= ~(1 << port);
  862. break;
  863. default:
  864. debug("unknown feature %x\n", le16_to_cpu(req->value));
  865. goto unknown;
  866. }
  867. ehci_writel(status_reg, reg);
  868. /* unblock posted write */
  869. (void) ehci_readl(&ctrl->hcor->or_usbcmd);
  870. break;
  871. default:
  872. debug("Unknown request\n");
  873. goto unknown;
  874. }
  875. mdelay(1);
  876. len = min3(srclen, (int)le16_to_cpu(req->length), length);
  877. if (srcptr != NULL && len > 0)
  878. memcpy(buffer, srcptr, len);
  879. else
  880. debug("Len is 0\n");
  881. dev->act_len = len;
  882. dev->status = 0;
  883. return 0;
  884. unknown:
  885. debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
  886. req->requesttype, req->request, le16_to_cpu(req->value),
  887. le16_to_cpu(req->index), le16_to_cpu(req->length));
  888. dev->act_len = 0;
  889. dev->status = USB_ST_STALLED;
  890. return -1;
  891. }
  892. const struct ehci_ops default_ehci_ops = {
  893. .set_usb_mode = ehci_set_usbmode,
  894. .get_port_speed = ehci_get_port_speed,
  895. .powerup_fixup = ehci_powerup_fixup,
  896. .get_portsc_register = ehci_get_portsc_register,
  897. };
  898. static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
  899. {
  900. if (!ops) {
  901. ctrl->ops = default_ehci_ops;
  902. } else {
  903. ctrl->ops = *ops;
  904. if (!ctrl->ops.set_usb_mode)
  905. ctrl->ops.set_usb_mode = ehci_set_usbmode;
  906. if (!ctrl->ops.get_port_speed)
  907. ctrl->ops.get_port_speed = ehci_get_port_speed;
  908. if (!ctrl->ops.powerup_fixup)
  909. ctrl->ops.powerup_fixup = ehci_powerup_fixup;
  910. if (!ctrl->ops.get_portsc_register)
  911. ctrl->ops.get_portsc_register =
  912. ehci_get_portsc_register;
  913. }
  914. }
  915. #ifndef CONFIG_DM_USB
  916. void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
  917. {
  918. struct ehci_ctrl *ctrl = &ehcic[index];
  919. ctrl->priv = priv;
  920. ehci_setup_ops(ctrl, ops);
  921. }
  922. void *ehci_get_controller_priv(int index)
  923. {
  924. return ehcic[index].priv;
  925. }
  926. #endif
  927. static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
  928. {
  929. struct QH *qh_list;
  930. struct QH *periodic;
  931. uint32_t reg;
  932. uint32_t cmd;
  933. int i;
  934. /* Set the high address word (aka segment) for 64-bit controller */
  935. if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
  936. ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
  937. qh_list = &ctrl->qh_list;
  938. /* Set head of reclaim list */
  939. memset(qh_list, 0, sizeof(*qh_list));
  940. qh_list->qh_link = cpu_to_hc32((unsigned long)qh_list | QH_LINK_TYPE_QH);
  941. qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
  942. QH_ENDPT1_EPS(USB_SPEED_HIGH));
  943. qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  944. qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  945. qh_list->qh_overlay.qt_token =
  946. cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
  947. flush_dcache_range((unsigned long)qh_list,
  948. ALIGN_END_ADDR(struct QH, qh_list, 1));
  949. /* Set async. queue head pointer. */
  950. ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)qh_list);
  951. /*
  952. * Set up periodic list
  953. * Step 1: Parent QH for all periodic transfers.
  954. */
  955. ctrl->periodic_schedules = 0;
  956. periodic = &ctrl->periodic_queue;
  957. memset(periodic, 0, sizeof(*periodic));
  958. periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
  959. periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  960. periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  961. flush_dcache_range((unsigned long)periodic,
  962. ALIGN_END_ADDR(struct QH, periodic, 1));
  963. /*
  964. * Step 2: Setup frame-list: Every microframe, USB tries the same list.
  965. * In particular, device specifications on polling frequency
  966. * are disregarded. Keyboards seem to send NAK/NYet reliably
  967. * when polled with an empty buffer.
  968. *
  969. * Split Transactions will be spread across microframes using
  970. * S-mask and C-mask.
  971. */
  972. if (ctrl->periodic_list == NULL)
  973. ctrl->periodic_list = memalign(4096, 1024 * 4);
  974. if (!ctrl->periodic_list)
  975. return -ENOMEM;
  976. for (i = 0; i < 1024; i++) {
  977. ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
  978. | QH_LINK_TYPE_QH);
  979. }
  980. flush_dcache_range((unsigned long)ctrl->periodic_list,
  981. ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
  982. 1024));
  983. /* Set periodic list base address */
  984. ehci_writel(&ctrl->hcor->or_periodiclistbase,
  985. (unsigned long)ctrl->periodic_list);
  986. reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
  987. descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
  988. debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
  989. /* Port Indicators */
  990. if (HCS_INDICATOR(reg))
  991. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  992. | 0x80, &descriptor.hub.wHubCharacteristics);
  993. /* Port Power Control */
  994. if (HCS_PPC(reg))
  995. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  996. | 0x01, &descriptor.hub.wHubCharacteristics);
  997. /* Start the host controller. */
  998. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  999. /*
  1000. * Philips, Intel, and maybe others need CMD_RUN before the
  1001. * root hub will detect new devices (why?); NEC doesn't
  1002. */
  1003. cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
  1004. cmd |= CMD_RUN;
  1005. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  1006. if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
  1007. /* take control over the ports */
  1008. cmd = ehci_readl(&ctrl->hcor->or_configflag);
  1009. cmd |= FLAG_CF;
  1010. ehci_writel(&ctrl->hcor->or_configflag, cmd);
  1011. }
  1012. /* unblock posted write */
  1013. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  1014. mdelay(5);
  1015. reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
  1016. printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
  1017. return 0;
  1018. }
  1019. #ifndef CONFIG_DM_USB
  1020. int usb_lowlevel_stop(int index)
  1021. {
  1022. ehci_shutdown(&ehcic[index]);
  1023. return ehci_hcd_stop(index);
  1024. }
  1025. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1026. {
  1027. struct ehci_ctrl *ctrl = &ehcic[index];
  1028. uint tweaks = 0;
  1029. int rc;
  1030. /**
  1031. * Set ops to default_ehci_ops, ehci_hcd_init should call
  1032. * ehci_set_controller_priv to change any of these function pointers.
  1033. */
  1034. ctrl->ops = default_ehci_ops;
  1035. rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
  1036. if (rc)
  1037. return rc;
  1038. if (init == USB_INIT_DEVICE)
  1039. goto done;
  1040. /* EHCI spec section 4.1 */
  1041. if (ehci_reset(ctrl))
  1042. return -1;
  1043. #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
  1044. rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
  1045. if (rc)
  1046. return rc;
  1047. #endif
  1048. #ifdef CONFIG_USB_EHCI_FARADAY
  1049. tweaks |= EHCI_TWEAK_NO_INIT_CF;
  1050. #endif
  1051. rc = ehci_common_init(ctrl, tweaks);
  1052. if (rc)
  1053. return rc;
  1054. ctrl->rootdev = 0;
  1055. done:
  1056. *controller = &ehcic[index];
  1057. return 0;
  1058. }
  1059. #endif
  1060. static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
  1061. void *buffer, int length)
  1062. {
  1063. if (usb_pipetype(pipe) != PIPE_BULK) {
  1064. debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
  1065. return -1;
  1066. }
  1067. return ehci_submit_async(dev, pipe, buffer, length, NULL);
  1068. }
  1069. static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
  1070. void *buffer, int length,
  1071. struct devrequest *setup)
  1072. {
  1073. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  1074. if (usb_pipetype(pipe) != PIPE_CONTROL) {
  1075. debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
  1076. return -1;
  1077. }
  1078. if (usb_pipedevice(pipe) == ctrl->rootdev) {
  1079. if (!ctrl->rootdev)
  1080. dev->speed = USB_SPEED_HIGH;
  1081. return ehci_submit_root(dev, pipe, buffer, length, setup);
  1082. }
  1083. return ehci_submit_async(dev, pipe, buffer, length, setup);
  1084. }
  1085. struct int_queue {
  1086. int elementsize;
  1087. unsigned long pipe;
  1088. struct QH *first;
  1089. struct QH *current;
  1090. struct QH *last;
  1091. struct qTD *tds;
  1092. };
  1093. #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
  1094. static int
  1095. enable_periodic(struct ehci_ctrl *ctrl)
  1096. {
  1097. uint32_t cmd;
  1098. struct ehci_hcor *hcor = ctrl->hcor;
  1099. int ret;
  1100. cmd = ehci_readl(&hcor->or_usbcmd);
  1101. cmd |= CMD_PSE;
  1102. ehci_writel(&hcor->or_usbcmd, cmd);
  1103. ret = handshake((uint32_t *)&hcor->or_usbsts,
  1104. STS_PSS, STS_PSS, 100 * 1000);
  1105. if (ret < 0) {
  1106. printf("EHCI failed: timeout when enabling periodic list\n");
  1107. return -ETIMEDOUT;
  1108. }
  1109. udelay(1000);
  1110. return 0;
  1111. }
  1112. static int
  1113. disable_periodic(struct ehci_ctrl *ctrl)
  1114. {
  1115. uint32_t cmd;
  1116. struct ehci_hcor *hcor = ctrl->hcor;
  1117. int ret;
  1118. cmd = ehci_readl(&hcor->or_usbcmd);
  1119. cmd &= ~CMD_PSE;
  1120. ehci_writel(&hcor->or_usbcmd, cmd);
  1121. ret = handshake((uint32_t *)&hcor->or_usbsts,
  1122. STS_PSS, 0, 100 * 1000);
  1123. if (ret < 0) {
  1124. printf("EHCI failed: timeout when disabling periodic list\n");
  1125. return -ETIMEDOUT;
  1126. }
  1127. return 0;
  1128. }
  1129. static struct int_queue *_ehci_create_int_queue(struct usb_device *dev,
  1130. unsigned long pipe, int queuesize, int elementsize,
  1131. void *buffer, int interval)
  1132. {
  1133. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  1134. struct int_queue *result = NULL;
  1135. uint32_t i, toggle;
  1136. /*
  1137. * Interrupt transfers requiring several transactions are not supported
  1138. * because bInterval is ignored.
  1139. *
  1140. * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
  1141. * <= PKT_ALIGN if several qTDs are required, while the USB
  1142. * specification does not constrain this for interrupt transfers. That
  1143. * means that ehci_submit_async() would support interrupt transfers
  1144. * requiring several transactions only as long as the transfer size does
  1145. * not require more than a single qTD.
  1146. */
  1147. if (elementsize > usb_maxpacket(dev, pipe)) {
  1148. printf("%s: xfers requiring several transactions are not supported.\n",
  1149. __func__);
  1150. return NULL;
  1151. }
  1152. debug("Enter create_int_queue\n");
  1153. if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
  1154. debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
  1155. return NULL;
  1156. }
  1157. /* limit to 4 full pages worth of data -
  1158. * we can safely fit them in a single TD,
  1159. * no matter the alignment
  1160. */
  1161. if (elementsize >= 16384) {
  1162. debug("too large elements for interrupt transfers\n");
  1163. return NULL;
  1164. }
  1165. result = malloc(sizeof(*result));
  1166. if (!result) {
  1167. debug("ehci intr queue: out of memory\n");
  1168. goto fail1;
  1169. }
  1170. result->elementsize = elementsize;
  1171. result->pipe = pipe;
  1172. result->first = memalign(USB_DMA_MINALIGN,
  1173. sizeof(struct QH) * queuesize);
  1174. if (!result->first) {
  1175. debug("ehci intr queue: out of memory\n");
  1176. goto fail2;
  1177. }
  1178. result->current = result->first;
  1179. result->last = result->first + queuesize - 1;
  1180. result->tds = memalign(USB_DMA_MINALIGN,
  1181. sizeof(struct qTD) * queuesize);
  1182. if (!result->tds) {
  1183. debug("ehci intr queue: out of memory\n");
  1184. goto fail3;
  1185. }
  1186. memset(result->first, 0, sizeof(struct QH) * queuesize);
  1187. memset(result->tds, 0, sizeof(struct qTD) * queuesize);
  1188. toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
  1189. for (i = 0; i < queuesize; i++) {
  1190. struct QH *qh = result->first + i;
  1191. struct qTD *td = result->tds + i;
  1192. void **buf = &qh->buffer;
  1193. qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
  1194. if (i == queuesize - 1)
  1195. qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
  1196. qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
  1197. qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  1198. qh->qh_endpt1 =
  1199. cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
  1200. (usb_maxpacket(dev, pipe) << 16) | /* MPS */
  1201. (1 << 14) |
  1202. QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
  1203. (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
  1204. (usb_pipedevice(pipe) << 0));
  1205. qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
  1206. (1 << 0)); /* S-mask: microframe 0 */
  1207. if (dev->speed == USB_SPEED_LOW ||
  1208. dev->speed == USB_SPEED_FULL) {
  1209. /* C-mask: microframes 2-4 */
  1210. qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
  1211. }
  1212. ehci_update_endpt2_dev_n_port(dev, qh);
  1213. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  1214. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  1215. debug("communication direction is '%s'\n",
  1216. usb_pipein(pipe) ? "in" : "out");
  1217. td->qt_token = cpu_to_hc32(
  1218. QT_TOKEN_DT(toggle) |
  1219. (elementsize << 16) |
  1220. ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
  1221. 0x80); /* active */
  1222. td->qt_buffer[0] =
  1223. cpu_to_hc32((unsigned long)buffer + i * elementsize);
  1224. td->qt_buffer[1] =
  1225. cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
  1226. td->qt_buffer[2] =
  1227. cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
  1228. td->qt_buffer[3] =
  1229. cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
  1230. td->qt_buffer[4] =
  1231. cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
  1232. *buf = buffer + i * elementsize;
  1233. toggle ^= 1;
  1234. }
  1235. flush_dcache_range((unsigned long)buffer,
  1236. ALIGN_END_ADDR(char, buffer,
  1237. queuesize * elementsize));
  1238. flush_dcache_range((unsigned long)result->first,
  1239. ALIGN_END_ADDR(struct QH, result->first,
  1240. queuesize));
  1241. flush_dcache_range((unsigned long)result->tds,
  1242. ALIGN_END_ADDR(struct qTD, result->tds,
  1243. queuesize));
  1244. if (ctrl->periodic_schedules > 0) {
  1245. if (disable_periodic(ctrl) < 0) {
  1246. debug("FATAL: periodic should never fail, but did");
  1247. goto fail3;
  1248. }
  1249. }
  1250. /* hook up to periodic list */
  1251. struct QH *list = &ctrl->periodic_queue;
  1252. result->last->qh_link = list->qh_link;
  1253. list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
  1254. flush_dcache_range((unsigned long)result->last,
  1255. ALIGN_END_ADDR(struct QH, result->last, 1));
  1256. flush_dcache_range((unsigned long)list,
  1257. ALIGN_END_ADDR(struct QH, list, 1));
  1258. if (enable_periodic(ctrl) < 0) {
  1259. debug("FATAL: periodic should never fail, but did");
  1260. goto fail3;
  1261. }
  1262. ctrl->periodic_schedules++;
  1263. debug("Exit create_int_queue\n");
  1264. return result;
  1265. fail3:
  1266. if (result->tds)
  1267. free(result->tds);
  1268. fail2:
  1269. if (result->first)
  1270. free(result->first);
  1271. if (result)
  1272. free(result);
  1273. fail1:
  1274. return NULL;
  1275. }
  1276. static void *_ehci_poll_int_queue(struct usb_device *dev,
  1277. struct int_queue *queue)
  1278. {
  1279. struct QH *cur = queue->current;
  1280. struct qTD *cur_td;
  1281. uint32_t token, toggle;
  1282. unsigned long pipe = queue->pipe;
  1283. /* depleted queue */
  1284. if (cur == NULL) {
  1285. debug("Exit poll_int_queue with completed queue\n");
  1286. return NULL;
  1287. }
  1288. /* still active */
  1289. cur_td = &queue->tds[queue->current - queue->first];
  1290. invalidate_dcache_range((unsigned long)cur_td,
  1291. ALIGN_END_ADDR(struct qTD, cur_td, 1));
  1292. token = hc32_to_cpu(cur_td->qt_token);
  1293. if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
  1294. debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token);
  1295. return NULL;
  1296. }
  1297. toggle = QT_TOKEN_GET_DT(token);
  1298. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
  1299. if (!(cur->qh_link & QH_LINK_TERMINATE))
  1300. queue->current++;
  1301. else
  1302. queue->current = NULL;
  1303. invalidate_dcache_range((unsigned long)cur->buffer,
  1304. ALIGN_END_ADDR(char, cur->buffer,
  1305. queue->elementsize));
  1306. debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
  1307. token, cur, queue->first);
  1308. return cur->buffer;
  1309. }
  1310. /* Do not free buffers associated with QHs, they're owned by someone else */
  1311. static int _ehci_destroy_int_queue(struct usb_device *dev,
  1312. struct int_queue *queue)
  1313. {
  1314. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  1315. int result = -1;
  1316. unsigned long timeout;
  1317. if (disable_periodic(ctrl) < 0) {
  1318. debug("FATAL: periodic should never fail, but did");
  1319. goto out;
  1320. }
  1321. ctrl->periodic_schedules--;
  1322. struct QH *cur = &ctrl->periodic_queue;
  1323. timeout = get_timer(0) + 500; /* abort after 500ms */
  1324. while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
  1325. debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
  1326. if (NEXT_QH(cur) == queue->first) {
  1327. debug("found candidate. removing from chain\n");
  1328. cur->qh_link = queue->last->qh_link;
  1329. flush_dcache_range((unsigned long)cur,
  1330. ALIGN_END_ADDR(struct QH, cur, 1));
  1331. result = 0;
  1332. break;
  1333. }
  1334. cur = NEXT_QH(cur);
  1335. if (get_timer(0) > timeout) {
  1336. printf("Timeout destroying interrupt endpoint queue\n");
  1337. result = -1;
  1338. goto out;
  1339. }
  1340. }
  1341. if (ctrl->periodic_schedules > 0) {
  1342. result = enable_periodic(ctrl);
  1343. if (result < 0)
  1344. debug("FATAL: periodic should never fail, but did");
  1345. }
  1346. out:
  1347. free(queue->tds);
  1348. free(queue->first);
  1349. free(queue);
  1350. return result;
  1351. }
  1352. static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
  1353. void *buffer, int length, int interval)
  1354. {
  1355. void *backbuffer;
  1356. struct int_queue *queue;
  1357. unsigned long timeout;
  1358. int result = 0, ret;
  1359. debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
  1360. dev, pipe, buffer, length, interval);
  1361. queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval);
  1362. if (!queue)
  1363. return -1;
  1364. timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
  1365. while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL)
  1366. if (get_timer(0) > timeout) {
  1367. printf("Timeout poll on interrupt endpoint\n");
  1368. result = -ETIMEDOUT;
  1369. break;
  1370. }
  1371. if (backbuffer != buffer) {
  1372. debug("got wrong buffer back (%p instead of %p)\n",
  1373. backbuffer, buffer);
  1374. return -EINVAL;
  1375. }
  1376. ret = _ehci_destroy_int_queue(dev, queue);
  1377. if (ret < 0)
  1378. return ret;
  1379. /* everything worked out fine */
  1380. return result;
  1381. }
  1382. #ifndef CONFIG_DM_USB
  1383. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
  1384. void *buffer, int length)
  1385. {
  1386. return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
  1387. }
  1388. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1389. int length, struct devrequest *setup)
  1390. {
  1391. return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
  1392. }
  1393. int submit_int_msg(struct usb_device *dev, unsigned long pipe,
  1394. void *buffer, int length, int interval)
  1395. {
  1396. return _ehci_submit_int_msg(dev, pipe, buffer, length, interval);
  1397. }
  1398. struct int_queue *create_int_queue(struct usb_device *dev,
  1399. unsigned long pipe, int queuesize, int elementsize,
  1400. void *buffer, int interval)
  1401. {
  1402. return _ehci_create_int_queue(dev, pipe, queuesize, elementsize,
  1403. buffer, interval);
  1404. }
  1405. void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
  1406. {
  1407. return _ehci_poll_int_queue(dev, queue);
  1408. }
  1409. int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
  1410. {
  1411. return _ehci_destroy_int_queue(dev, queue);
  1412. }
  1413. #endif
  1414. #ifdef CONFIG_DM_USB
  1415. static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
  1416. unsigned long pipe, void *buffer, int length,
  1417. struct devrequest *setup)
  1418. {
  1419. debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
  1420. dev->name, udev, udev->dev->name, udev->portnr);
  1421. return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
  1422. }
  1423. static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
  1424. unsigned long pipe, void *buffer, int length)
  1425. {
  1426. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1427. return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
  1428. }
  1429. static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
  1430. unsigned long pipe, void *buffer, int length,
  1431. int interval)
  1432. {
  1433. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1434. return _ehci_submit_int_msg(udev, pipe, buffer, length, interval);
  1435. }
  1436. static struct int_queue *ehci_create_int_queue(struct udevice *dev,
  1437. struct usb_device *udev, unsigned long pipe, int queuesize,
  1438. int elementsize, void *buffer, int interval)
  1439. {
  1440. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1441. return _ehci_create_int_queue(udev, pipe, queuesize, elementsize,
  1442. buffer, interval);
  1443. }
  1444. static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
  1445. struct int_queue *queue)
  1446. {
  1447. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1448. return _ehci_poll_int_queue(udev, queue);
  1449. }
  1450. static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
  1451. struct int_queue *queue)
  1452. {
  1453. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1454. return _ehci_destroy_int_queue(udev, queue);
  1455. }
  1456. int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
  1457. struct ehci_hcor *hcor, const struct ehci_ops *ops,
  1458. uint tweaks, enum usb_init_type init)
  1459. {
  1460. struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
  1461. struct ehci_ctrl *ctrl = dev_get_priv(dev);
  1462. int ret;
  1463. debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
  1464. dev->name, ctrl, hccr, hcor, init);
  1465. priv->desc_before_addr = true;
  1466. ehci_setup_ops(ctrl, ops);
  1467. ctrl->hccr = hccr;
  1468. ctrl->hcor = hcor;
  1469. ctrl->priv = ctrl;
  1470. ctrl->init = init;
  1471. if (ctrl->init == USB_INIT_DEVICE)
  1472. goto done;
  1473. ret = ehci_reset(ctrl);
  1474. if (ret)
  1475. goto err;
  1476. ret = ehci_common_init(ctrl, tweaks);
  1477. if (ret)
  1478. goto err;
  1479. done:
  1480. return 0;
  1481. err:
  1482. free(ctrl);
  1483. debug("%s: failed, ret=%d\n", __func__, ret);
  1484. return ret;
  1485. }
  1486. int ehci_deregister(struct udevice *dev)
  1487. {
  1488. struct ehci_ctrl *ctrl = dev_get_priv(dev);
  1489. if (ctrl->init == USB_INIT_DEVICE)
  1490. return 0;
  1491. ehci_shutdown(ctrl);
  1492. return 0;
  1493. }
  1494. struct dm_usb_ops ehci_usb_ops = {
  1495. .control = ehci_submit_control_msg,
  1496. .bulk = ehci_submit_bulk_msg,
  1497. .interrupt = ehci_submit_int_msg,
  1498. .create_int_queue = ehci_create_int_queue,
  1499. .poll_int_queue = ehci_poll_int_queue,
  1500. .destroy_int_queue = ehci_destroy_int_queue,
  1501. };
  1502. #endif