smsc95xx.c 26 KB

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  1. /*
  2. * Copyright (c) 2015 Google, Inc
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * Copyright (C) 2009 NVIDIA, Corporation
  5. * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <malloc.h>
  13. #include <memalign.h>
  14. #include <usb.h>
  15. #include <asm/unaligned.h>
  16. #include <linux/mii.h>
  17. #include "usb_ether.h"
  18. /* SMSC LAN95xx based USB 2.0 Ethernet Devices */
  19. /* LED defines */
  20. #define LED_GPIO_CFG (0x24)
  21. #define LED_GPIO_CFG_SPD_LED (0x01000000)
  22. #define LED_GPIO_CFG_LNK_LED (0x00100000)
  23. #define LED_GPIO_CFG_FDX_LED (0x00010000)
  24. /* Tx command words */
  25. #define TX_CMD_A_FIRST_SEG_ 0x00002000
  26. #define TX_CMD_A_LAST_SEG_ 0x00001000
  27. /* Rx status word */
  28. #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
  29. #define RX_STS_ES_ 0x00008000 /* Error Summary */
  30. /* SCSRs */
  31. #define ID_REV 0x00
  32. #define INT_STS 0x08
  33. #define TX_CFG 0x10
  34. #define TX_CFG_ON_ 0x00000004
  35. #define HW_CFG 0x14
  36. #define HW_CFG_BIR_ 0x00001000
  37. #define HW_CFG_RXDOFF_ 0x00000600
  38. #define HW_CFG_MEF_ 0x00000020
  39. #define HW_CFG_BCE_ 0x00000002
  40. #define HW_CFG_LRST_ 0x00000008
  41. #define PM_CTRL 0x20
  42. #define PM_CTL_PHY_RST_ 0x00000010
  43. #define AFC_CFG 0x2C
  44. /*
  45. * Hi watermark = 15.5Kb (~10 mtu pkts)
  46. * low watermark = 3k (~2 mtu pkts)
  47. * backpressure duration = ~ 350us
  48. * Apply FC on any frame.
  49. */
  50. #define AFC_CFG_DEFAULT 0x00F830A1
  51. #define E2P_CMD 0x30
  52. #define E2P_CMD_BUSY_ 0x80000000
  53. #define E2P_CMD_READ_ 0x00000000
  54. #define E2P_CMD_TIMEOUT_ 0x00000400
  55. #define E2P_CMD_LOADED_ 0x00000200
  56. #define E2P_CMD_ADDR_ 0x000001FF
  57. #define E2P_DATA 0x34
  58. #define BURST_CAP 0x38
  59. #define INT_EP_CTL 0x68
  60. #define INT_EP_CTL_PHY_INT_ 0x00008000
  61. #define BULK_IN_DLY 0x6C
  62. /* MAC CSRs */
  63. #define MAC_CR 0x100
  64. #define MAC_CR_MCPAS_ 0x00080000
  65. #define MAC_CR_PRMS_ 0x00040000
  66. #define MAC_CR_HPFILT_ 0x00002000
  67. #define MAC_CR_TXEN_ 0x00000008
  68. #define MAC_CR_RXEN_ 0x00000004
  69. #define ADDRH 0x104
  70. #define ADDRL 0x108
  71. #define MII_ADDR 0x114
  72. #define MII_WRITE_ 0x02
  73. #define MII_BUSY_ 0x01
  74. #define MII_READ_ 0x00 /* ~of MII Write bit */
  75. #define MII_DATA 0x118
  76. #define FLOW 0x11C
  77. #define VLAN1 0x120
  78. #define COE_CR 0x130
  79. #define Tx_COE_EN_ 0x00010000
  80. #define Rx_COE_EN_ 0x00000001
  81. /* Vendor-specific PHY Definitions */
  82. #define PHY_INT_SRC 29
  83. #define PHY_INT_MASK 30
  84. #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
  85. #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
  86. #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
  87. PHY_INT_MASK_LINK_DOWN_)
  88. /* USB Vendor Requests */
  89. #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
  90. #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
  91. /* Some extra defines */
  92. #define HS_USB_PKT_SIZE 512
  93. #define FS_USB_PKT_SIZE 64
  94. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  95. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  96. #define DEFAULT_BULK_IN_DELAY 0x00002000
  97. #define MAX_SINGLE_PACKET_SIZE 2048
  98. #define EEPROM_MAC_OFFSET 0x01
  99. #define SMSC95XX_INTERNAL_PHY_ID 1
  100. #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
  101. /* local defines */
  102. #define SMSC95XX_BASE_NAME "sms"
  103. #define USB_CTRL_SET_TIMEOUT 5000
  104. #define USB_CTRL_GET_TIMEOUT 5000
  105. #define USB_BULK_SEND_TIMEOUT 5000
  106. #define USB_BULK_RECV_TIMEOUT 5000
  107. #define RX_URB_SIZE 2048
  108. #define PHY_CONNECT_TIMEOUT 5000
  109. #define TURBO_MODE
  110. #ifndef CONFIG_DM_ETH
  111. /* local vars */
  112. static int curr_eth_dev; /* index for name of next device detected */
  113. #endif
  114. /* driver private */
  115. struct smsc95xx_private {
  116. #ifdef CONFIG_DM_ETH
  117. struct ueth_data ueth;
  118. #endif
  119. size_t rx_urb_size; /* maximum USB URB size */
  120. u32 mac_cr; /* MAC control register value */
  121. int have_hwaddr; /* 1 if we have a hardware MAC address */
  122. };
  123. /*
  124. * Smsc95xx infrastructure commands
  125. */
  126. static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data)
  127. {
  128. int len;
  129. ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
  130. cpu_to_le32s(&data);
  131. tmpbuf[0] = data;
  132. len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
  133. USB_VENDOR_REQUEST_WRITE_REGISTER,
  134. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  135. 0, index, tmpbuf, sizeof(data),
  136. USB_CTRL_SET_TIMEOUT);
  137. if (len != sizeof(data)) {
  138. debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
  139. index, data, len);
  140. return -EIO;
  141. }
  142. return 0;
  143. }
  144. static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data)
  145. {
  146. int len;
  147. ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
  148. len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
  149. USB_VENDOR_REQUEST_READ_REGISTER,
  150. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  151. 0, index, tmpbuf, sizeof(data),
  152. USB_CTRL_GET_TIMEOUT);
  153. *data = tmpbuf[0];
  154. if (len != sizeof(data)) {
  155. debug("smsc95xx_read_reg failed: index=%d, len=%d",
  156. index, len);
  157. return -EIO;
  158. }
  159. le32_to_cpus(data);
  160. return 0;
  161. }
  162. /* Loop until the read is completed with timeout */
  163. static int smsc95xx_phy_wait_not_busy(struct usb_device *udev)
  164. {
  165. unsigned long start_time = get_timer(0);
  166. u32 val;
  167. do {
  168. smsc95xx_read_reg(udev, MII_ADDR, &val);
  169. if (!(val & MII_BUSY_))
  170. return 0;
  171. } while (get_timer(start_time) < 1000);
  172. return -ETIMEDOUT;
  173. }
  174. static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx)
  175. {
  176. u32 val, addr;
  177. /* confirm MII not busy */
  178. if (smsc95xx_phy_wait_not_busy(udev)) {
  179. debug("MII is busy in smsc95xx_mdio_read\n");
  180. return -ETIMEDOUT;
  181. }
  182. /* set the address, index & direction (read from PHY) */
  183. addr = (phy_id << 11) | (idx << 6) | MII_READ_;
  184. smsc95xx_write_reg(udev, MII_ADDR, addr);
  185. if (smsc95xx_phy_wait_not_busy(udev)) {
  186. debug("Timed out reading MII reg %02X\n", idx);
  187. return -ETIMEDOUT;
  188. }
  189. smsc95xx_read_reg(udev, MII_DATA, &val);
  190. return (u16)(val & 0xFFFF);
  191. }
  192. static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx,
  193. int regval)
  194. {
  195. u32 val, addr;
  196. /* confirm MII not busy */
  197. if (smsc95xx_phy_wait_not_busy(udev)) {
  198. debug("MII is busy in smsc95xx_mdio_write\n");
  199. return;
  200. }
  201. val = regval;
  202. smsc95xx_write_reg(udev, MII_DATA, val);
  203. /* set the address, index & direction (write to PHY) */
  204. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
  205. smsc95xx_write_reg(udev, MII_ADDR, addr);
  206. if (smsc95xx_phy_wait_not_busy(udev))
  207. debug("Timed out writing MII reg %02X\n", idx);
  208. }
  209. static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev)
  210. {
  211. unsigned long start_time = get_timer(0);
  212. u32 val;
  213. do {
  214. smsc95xx_read_reg(udev, E2P_CMD, &val);
  215. if (!(val & E2P_CMD_BUSY_))
  216. return 0;
  217. udelay(40);
  218. } while (get_timer(start_time) < 1 * 1000 * 1000);
  219. debug("EEPROM is busy\n");
  220. return -ETIMEDOUT;
  221. }
  222. static int smsc95xx_wait_eeprom(struct usb_device *udev)
  223. {
  224. unsigned long start_time = get_timer(0);
  225. u32 val;
  226. do {
  227. smsc95xx_read_reg(udev, E2P_CMD, &val);
  228. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  229. break;
  230. udelay(40);
  231. } while (get_timer(start_time) < 1 * 1000 * 1000);
  232. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  233. debug("EEPROM read operation timeout\n");
  234. return -ETIMEDOUT;
  235. }
  236. return 0;
  237. }
  238. static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length,
  239. u8 *data)
  240. {
  241. u32 val;
  242. int i, ret;
  243. ret = smsc95xx_eeprom_confirm_not_busy(udev);
  244. if (ret)
  245. return ret;
  246. for (i = 0; i < length; i++) {
  247. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  248. smsc95xx_write_reg(udev, E2P_CMD, val);
  249. ret = smsc95xx_wait_eeprom(udev);
  250. if (ret < 0)
  251. return ret;
  252. smsc95xx_read_reg(udev, E2P_DATA, &val);
  253. data[i] = val & 0xFF;
  254. offset++;
  255. }
  256. return 0;
  257. }
  258. /*
  259. * mii_nway_restart - restart NWay (autonegotiation) for this interface
  260. *
  261. * Returns 0 on success, negative on error.
  262. */
  263. static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev)
  264. {
  265. int bmcr;
  266. int r = -1;
  267. /* if autoneg is off, it's an error */
  268. bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR);
  269. if (bmcr & BMCR_ANENABLE) {
  270. bmcr |= BMCR_ANRESTART;
  271. smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr);
  272. r = 0;
  273. }
  274. return r;
  275. }
  276. static int smsc95xx_phy_initialize(struct usb_device *udev,
  277. struct ueth_data *dev)
  278. {
  279. smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET);
  280. smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE,
  281. ADVERTISE_ALL | ADVERTISE_CSMA |
  282. ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  283. /* read to clear */
  284. smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC);
  285. smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK,
  286. PHY_INT_MASK_DEFAULT_);
  287. mii_nway_restart(udev, dev);
  288. debug("phy initialised succesfully\n");
  289. return 0;
  290. }
  291. static int smsc95xx_init_mac_address(unsigned char *enetaddr,
  292. struct usb_device *udev)
  293. {
  294. int ret;
  295. /* try reading mac address from EEPROM */
  296. ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr);
  297. if (ret)
  298. return ret;
  299. if (is_valid_ethaddr(enetaddr)) {
  300. /* eeprom values are valid so use them */
  301. debug("MAC address read from EEPROM\n");
  302. return 0;
  303. }
  304. /*
  305. * No eeprom, or eeprom values are invalid. Generating a random MAC
  306. * address is not safe. Just return an error.
  307. */
  308. debug("Invalid MAC address read from EEPROM\n");
  309. return -ENXIO;
  310. }
  311. static int smsc95xx_write_hwaddr_common(struct usb_device *udev,
  312. struct smsc95xx_private *priv,
  313. unsigned char *enetaddr)
  314. {
  315. u32 addr_lo = __get_unaligned_le32(&enetaddr[0]);
  316. u32 addr_hi = __get_unaligned_le16(&enetaddr[4]);
  317. int ret;
  318. /* set hardware address */
  319. debug("** %s()\n", __func__);
  320. ret = smsc95xx_write_reg(udev, ADDRL, addr_lo);
  321. if (ret < 0)
  322. return ret;
  323. ret = smsc95xx_write_reg(udev, ADDRH, addr_hi);
  324. if (ret < 0)
  325. return ret;
  326. debug("MAC %pM\n", enetaddr);
  327. priv->have_hwaddr = 1;
  328. return 0;
  329. }
  330. /* Enable or disable Tx & Rx checksum offload engines */
  331. static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum,
  332. int use_rx_csum)
  333. {
  334. u32 read_buf;
  335. int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf);
  336. if (ret < 0)
  337. return ret;
  338. if (use_tx_csum)
  339. read_buf |= Tx_COE_EN_;
  340. else
  341. read_buf &= ~Tx_COE_EN_;
  342. if (use_rx_csum)
  343. read_buf |= Rx_COE_EN_;
  344. else
  345. read_buf &= ~Rx_COE_EN_;
  346. ret = smsc95xx_write_reg(udev, COE_CR, read_buf);
  347. if (ret < 0)
  348. return ret;
  349. debug("COE_CR = 0x%08x\n", read_buf);
  350. return 0;
  351. }
  352. static void smsc95xx_set_multicast(struct smsc95xx_private *priv)
  353. {
  354. /* No multicast in u-boot */
  355. priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  356. }
  357. /* starts the TX path */
  358. static void smsc95xx_start_tx_path(struct usb_device *udev,
  359. struct smsc95xx_private *priv)
  360. {
  361. u32 reg_val;
  362. /* Enable Tx at MAC */
  363. priv->mac_cr |= MAC_CR_TXEN_;
  364. smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
  365. /* Enable Tx at SCSRs */
  366. reg_val = TX_CFG_ON_;
  367. smsc95xx_write_reg(udev, TX_CFG, reg_val);
  368. }
  369. /* Starts the Receive path */
  370. static void smsc95xx_start_rx_path(struct usb_device *udev,
  371. struct smsc95xx_private *priv)
  372. {
  373. priv->mac_cr |= MAC_CR_RXEN_;
  374. smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
  375. }
  376. static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
  377. struct smsc95xx_private *priv,
  378. unsigned char *enetaddr)
  379. {
  380. int ret;
  381. u32 write_buf;
  382. u32 read_buf;
  383. u32 burst_cap;
  384. int timeout;
  385. #define TIMEOUT_RESOLUTION 50 /* ms */
  386. int link_detected;
  387. debug("** %s()\n", __func__);
  388. dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
  389. write_buf = HW_CFG_LRST_;
  390. ret = smsc95xx_write_reg(udev, HW_CFG, write_buf);
  391. if (ret < 0)
  392. return ret;
  393. timeout = 0;
  394. do {
  395. ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
  396. if (ret < 0)
  397. return ret;
  398. udelay(10 * 1000);
  399. timeout++;
  400. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  401. if (timeout >= 100) {
  402. debug("timeout waiting for completion of Lite Reset\n");
  403. return -ETIMEDOUT;
  404. }
  405. write_buf = PM_CTL_PHY_RST_;
  406. ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf);
  407. if (ret < 0)
  408. return ret;
  409. timeout = 0;
  410. do {
  411. ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf);
  412. if (ret < 0)
  413. return ret;
  414. udelay(10 * 1000);
  415. timeout++;
  416. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  417. if (timeout >= 100) {
  418. debug("timeout waiting for PHY Reset\n");
  419. return -ETIMEDOUT;
  420. }
  421. if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) ==
  422. 0)
  423. priv->have_hwaddr = 1;
  424. if (!priv->have_hwaddr) {
  425. puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
  426. return -EADDRNOTAVAIL;
  427. }
  428. ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr);
  429. if (ret < 0)
  430. return ret;
  431. ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
  432. if (ret < 0)
  433. return ret;
  434. debug("Read Value from HW_CFG : 0x%08x\n", read_buf);
  435. read_buf |= HW_CFG_BIR_;
  436. ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
  437. if (ret < 0)
  438. return ret;
  439. ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
  440. if (ret < 0)
  441. return ret;
  442. debug("Read Value from HW_CFG after writing "
  443. "HW_CFG_BIR_: 0x%08x\n", read_buf);
  444. #ifdef TURBO_MODE
  445. if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
  446. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  447. priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  448. } else {
  449. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  450. priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  451. }
  452. #else
  453. burst_cap = 0;
  454. priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  455. #endif
  456. debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
  457. ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap);
  458. if (ret < 0)
  459. return ret;
  460. ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf);
  461. if (ret < 0)
  462. return ret;
  463. debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
  464. read_buf = DEFAULT_BULK_IN_DELAY;
  465. ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf);
  466. if (ret < 0)
  467. return ret;
  468. ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf);
  469. if (ret < 0)
  470. return ret;
  471. debug("Read Value from BULK_IN_DLY after writing: "
  472. "0x%08x\n", read_buf);
  473. ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
  474. if (ret < 0)
  475. return ret;
  476. debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
  477. #ifdef TURBO_MODE
  478. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  479. #endif
  480. read_buf &= ~HW_CFG_RXDOFF_;
  481. #define NET_IP_ALIGN 0
  482. read_buf |= NET_IP_ALIGN << 9;
  483. ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
  484. if (ret < 0)
  485. return ret;
  486. ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
  487. if (ret < 0)
  488. return ret;
  489. debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
  490. write_buf = 0xFFFFFFFF;
  491. ret = smsc95xx_write_reg(udev, INT_STS, write_buf);
  492. if (ret < 0)
  493. return ret;
  494. ret = smsc95xx_read_reg(udev, ID_REV, &read_buf);
  495. if (ret < 0)
  496. return ret;
  497. debug("ID_REV = 0x%08x\n", read_buf);
  498. /* Configure GPIO pins as LED outputs */
  499. write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
  500. LED_GPIO_CFG_FDX_LED;
  501. ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf);
  502. if (ret < 0)
  503. return ret;
  504. debug("LED_GPIO_CFG set\n");
  505. /* Init Tx */
  506. write_buf = 0;
  507. ret = smsc95xx_write_reg(udev, FLOW, write_buf);
  508. if (ret < 0)
  509. return ret;
  510. read_buf = AFC_CFG_DEFAULT;
  511. ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf);
  512. if (ret < 0)
  513. return ret;
  514. ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr);
  515. if (ret < 0)
  516. return ret;
  517. /* Init Rx. Set Vlan */
  518. write_buf = (u32)ETH_P_8021Q;
  519. ret = smsc95xx_write_reg(udev, VLAN1, write_buf);
  520. if (ret < 0)
  521. return ret;
  522. /* Disable checksum offload engines */
  523. ret = smsc95xx_set_csums(udev, 0, 0);
  524. if (ret < 0) {
  525. debug("Failed to set csum offload: %d\n", ret);
  526. return ret;
  527. }
  528. smsc95xx_set_multicast(priv);
  529. ret = smsc95xx_phy_initialize(udev, dev);
  530. if (ret < 0)
  531. return ret;
  532. ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf);
  533. if (ret < 0)
  534. return ret;
  535. /* enable PHY interrupts */
  536. read_buf |= INT_EP_CTL_PHY_INT_;
  537. ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf);
  538. if (ret < 0)
  539. return ret;
  540. smsc95xx_start_tx_path(udev, priv);
  541. smsc95xx_start_rx_path(udev, priv);
  542. timeout = 0;
  543. do {
  544. link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR)
  545. & BMSR_LSTATUS;
  546. if (!link_detected) {
  547. if (timeout == 0)
  548. printf("Waiting for Ethernet connection... ");
  549. udelay(TIMEOUT_RESOLUTION * 1000);
  550. timeout += TIMEOUT_RESOLUTION;
  551. }
  552. } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
  553. if (link_detected) {
  554. if (timeout != 0)
  555. printf("done.\n");
  556. } else {
  557. printf("unable to connect.\n");
  558. return -EIO;
  559. }
  560. return 0;
  561. }
  562. static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
  563. {
  564. int err;
  565. int actual_len;
  566. u32 tx_cmd_a;
  567. u32 tx_cmd_b;
  568. ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
  569. PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
  570. debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg);
  571. if (length > PKTSIZE)
  572. return -ENOSPC;
  573. tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  574. tx_cmd_b = (u32)length;
  575. cpu_to_le32s(&tx_cmd_a);
  576. cpu_to_le32s(&tx_cmd_b);
  577. /* prepend cmd_a and cmd_b */
  578. memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
  579. memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
  580. memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
  581. length);
  582. err = usb_bulk_msg(dev->pusb_dev,
  583. usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
  584. (void *)msg,
  585. length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
  586. &actual_len,
  587. USB_BULK_SEND_TIMEOUT);
  588. debug("Tx: len = %u, actual = %u, err = %d\n",
  589. length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
  590. actual_len, err);
  591. return err;
  592. }
  593. #ifndef CONFIG_DM_ETH
  594. /*
  595. * Smsc95xx callbacks
  596. */
  597. static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
  598. {
  599. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  600. struct usb_device *udev = dev->pusb_dev;
  601. struct smsc95xx_private *priv =
  602. (struct smsc95xx_private *)dev->dev_priv;
  603. return smsc95xx_init_common(udev, dev, priv, eth->enetaddr);
  604. }
  605. static int smsc95xx_send(struct eth_device *eth, void *packet, int length)
  606. {
  607. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  608. return smsc95xx_send_common(dev, packet, length);
  609. }
  610. static int smsc95xx_recv(struct eth_device *eth)
  611. {
  612. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  613. DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE);
  614. unsigned char *buf_ptr;
  615. int err;
  616. int actual_len;
  617. u32 packet_len;
  618. int cur_buf_align;
  619. debug("** %s()\n", __func__);
  620. err = usb_bulk_msg(dev->pusb_dev,
  621. usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
  622. (void *)recv_buf, RX_URB_SIZE, &actual_len,
  623. USB_BULK_RECV_TIMEOUT);
  624. debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE,
  625. actual_len, err);
  626. if (err != 0) {
  627. debug("Rx: failed to receive\n");
  628. return -err;
  629. }
  630. if (actual_len > RX_URB_SIZE) {
  631. debug("Rx: received too many bytes %d\n", actual_len);
  632. return -ENOSPC;
  633. }
  634. buf_ptr = recv_buf;
  635. while (actual_len > 0) {
  636. /*
  637. * 1st 4 bytes contain the length of the actual data plus error
  638. * info. Extract data length.
  639. */
  640. if (actual_len < sizeof(packet_len)) {
  641. debug("Rx: incomplete packet length\n");
  642. return -EIO;
  643. }
  644. memcpy(&packet_len, buf_ptr, sizeof(packet_len));
  645. le32_to_cpus(&packet_len);
  646. if (packet_len & RX_STS_ES_) {
  647. debug("Rx: Error header=%#x", packet_len);
  648. return -EIO;
  649. }
  650. packet_len = ((packet_len & RX_STS_FL_) >> 16);
  651. if (packet_len > actual_len - sizeof(packet_len)) {
  652. debug("Rx: too large packet: %d\n", packet_len);
  653. return -EIO;
  654. }
  655. /* Notify net stack */
  656. net_process_received_packet(buf_ptr + sizeof(packet_len),
  657. packet_len - 4);
  658. /* Adjust for next iteration */
  659. actual_len -= sizeof(packet_len) + packet_len;
  660. buf_ptr += sizeof(packet_len) + packet_len;
  661. cur_buf_align = (int)buf_ptr - (int)recv_buf;
  662. if (cur_buf_align & 0x03) {
  663. int align = 4 - (cur_buf_align & 0x03);
  664. actual_len -= align;
  665. buf_ptr += align;
  666. }
  667. }
  668. return err;
  669. }
  670. static void smsc95xx_halt(struct eth_device *eth)
  671. {
  672. debug("** %s()\n", __func__);
  673. }
  674. static int smsc95xx_write_hwaddr(struct eth_device *eth)
  675. {
  676. struct ueth_data *dev = eth->priv;
  677. struct usb_device *udev = dev->pusb_dev;
  678. struct smsc95xx_private *priv = dev->dev_priv;
  679. return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr);
  680. }
  681. /*
  682. * SMSC probing functions
  683. */
  684. void smsc95xx_eth_before_probe(void)
  685. {
  686. curr_eth_dev = 0;
  687. }
  688. struct smsc95xx_dongle {
  689. unsigned short vendor;
  690. unsigned short product;
  691. };
  692. static const struct smsc95xx_dongle smsc95xx_dongles[] = {
  693. { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
  694. { 0x0424, 0x9500 }, /* LAN9500 Ethernet */
  695. { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */
  696. { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */
  697. { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */
  698. { 0x0000, 0x0000 } /* END - Do not remove */
  699. };
  700. /* Probe to see if a new device is actually an SMSC device */
  701. int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
  702. struct ueth_data *ss)
  703. {
  704. struct usb_interface *iface;
  705. struct usb_interface_descriptor *iface_desc;
  706. int i;
  707. /* let's examine the device now */
  708. iface = &dev->config.if_desc[ifnum];
  709. iface_desc = &dev->config.if_desc[ifnum].desc;
  710. for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
  711. if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
  712. dev->descriptor.idProduct == smsc95xx_dongles[i].product)
  713. /* Found a supported dongle */
  714. break;
  715. }
  716. if (smsc95xx_dongles[i].vendor == 0)
  717. return 0;
  718. /* At this point, we know we've got a live one */
  719. debug("\n\nUSB Ethernet device detected\n");
  720. memset(ss, '\0', sizeof(struct ueth_data));
  721. /* Initialize the ueth_data structure with some useful info */
  722. ss->ifnum = ifnum;
  723. ss->pusb_dev = dev;
  724. ss->subclass = iface_desc->bInterfaceSubClass;
  725. ss->protocol = iface_desc->bInterfaceProtocol;
  726. /*
  727. * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
  728. * We will ignore any others.
  729. */
  730. for (i = 0; i < iface_desc->bNumEndpoints; i++) {
  731. /* is it an BULK endpoint? */
  732. if ((iface->ep_desc[i].bmAttributes &
  733. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
  734. if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
  735. ss->ep_in =
  736. iface->ep_desc[i].bEndpointAddress &
  737. USB_ENDPOINT_NUMBER_MASK;
  738. else
  739. ss->ep_out =
  740. iface->ep_desc[i].bEndpointAddress &
  741. USB_ENDPOINT_NUMBER_MASK;
  742. }
  743. /* is it an interrupt endpoint? */
  744. if ((iface->ep_desc[i].bmAttributes &
  745. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
  746. ss->ep_int = iface->ep_desc[i].bEndpointAddress &
  747. USB_ENDPOINT_NUMBER_MASK;
  748. ss->irqinterval = iface->ep_desc[i].bInterval;
  749. }
  750. }
  751. debug("Endpoints In %d Out %d Int %d\n",
  752. ss->ep_in, ss->ep_out, ss->ep_int);
  753. /* Do some basic sanity checks, and bail if we find a problem */
  754. if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
  755. !ss->ep_in || !ss->ep_out || !ss->ep_int) {
  756. debug("Problems with device\n");
  757. return 0;
  758. }
  759. dev->privptr = (void *)ss;
  760. /* alloc driver private */
  761. ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
  762. if (!ss->dev_priv)
  763. return 0;
  764. return 1;
  765. }
  766. int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
  767. struct eth_device *eth)
  768. {
  769. debug("** %s()\n", __func__);
  770. if (!eth) {
  771. debug("%s: missing parameter.\n", __func__);
  772. return 0;
  773. }
  774. sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
  775. eth->init = smsc95xx_init;
  776. eth->send = smsc95xx_send;
  777. eth->recv = smsc95xx_recv;
  778. eth->halt = smsc95xx_halt;
  779. eth->write_hwaddr = smsc95xx_write_hwaddr;
  780. eth->priv = ss;
  781. return 1;
  782. }
  783. #endif /* !CONFIG_DM_ETH */
  784. #ifdef CONFIG_DM_ETH
  785. static int smsc95xx_eth_start(struct udevice *dev)
  786. {
  787. struct usb_device *udev = dev_get_parent_priv(dev);
  788. struct smsc95xx_private *priv = dev_get_priv(dev);
  789. struct eth_pdata *pdata = dev_get_platdata(dev);
  790. /* Driver-model Ethernet ensures we have this */
  791. priv->have_hwaddr = 1;
  792. return smsc95xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr);
  793. }
  794. void smsc95xx_eth_stop(struct udevice *dev)
  795. {
  796. debug("** %s()\n", __func__);
  797. }
  798. int smsc95xx_eth_send(struct udevice *dev, void *packet, int length)
  799. {
  800. struct smsc95xx_private *priv = dev_get_priv(dev);
  801. return smsc95xx_send_common(&priv->ueth, packet, length);
  802. }
  803. int smsc95xx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  804. {
  805. struct smsc95xx_private *priv = dev_get_priv(dev);
  806. struct ueth_data *ueth = &priv->ueth;
  807. uint8_t *ptr;
  808. int ret, len;
  809. u32 packet_len;
  810. len = usb_ether_get_rx_bytes(ueth, &ptr);
  811. debug("%s: first try, len=%d\n", __func__, len);
  812. if (!len) {
  813. if (!(flags & ETH_RECV_CHECK_DEVICE))
  814. return -EAGAIN;
  815. ret = usb_ether_receive(ueth, RX_URB_SIZE);
  816. if (ret == -EAGAIN)
  817. return ret;
  818. len = usb_ether_get_rx_bytes(ueth, &ptr);
  819. debug("%s: second try, len=%d\n", __func__, len);
  820. }
  821. /*
  822. * 1st 4 bytes contain the length of the actual data plus error info.
  823. * Extract data length.
  824. */
  825. if (len < sizeof(packet_len)) {
  826. debug("Rx: incomplete packet length\n");
  827. goto err;
  828. }
  829. memcpy(&packet_len, ptr, sizeof(packet_len));
  830. le32_to_cpus(&packet_len);
  831. if (packet_len & RX_STS_ES_) {
  832. debug("Rx: Error header=%#x", packet_len);
  833. goto err;
  834. }
  835. packet_len = ((packet_len & RX_STS_FL_) >> 16);
  836. if (packet_len > len - sizeof(packet_len)) {
  837. debug("Rx: too large packet: %d\n", packet_len);
  838. goto err;
  839. }
  840. *packetp = ptr + sizeof(packet_len);
  841. return packet_len;
  842. err:
  843. usb_ether_advance_rxbuf(ueth, -1);
  844. return -EINVAL;
  845. }
  846. static int smsc95xx_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
  847. {
  848. struct smsc95xx_private *priv = dev_get_priv(dev);
  849. packet_len = ALIGN(packet_len, 4);
  850. usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
  851. return 0;
  852. }
  853. int smsc95xx_write_hwaddr(struct udevice *dev)
  854. {
  855. struct usb_device *udev = dev_get_parent_priv(dev);
  856. struct eth_pdata *pdata = dev_get_platdata(dev);
  857. struct smsc95xx_private *priv = dev_get_priv(dev);
  858. return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr);
  859. }
  860. static int smsc95xx_eth_probe(struct udevice *dev)
  861. {
  862. struct smsc95xx_private *priv = dev_get_priv(dev);
  863. struct ueth_data *ueth = &priv->ueth;
  864. return usb_ether_register(dev, ueth, RX_URB_SIZE);
  865. }
  866. static const struct eth_ops smsc95xx_eth_ops = {
  867. .start = smsc95xx_eth_start,
  868. .send = smsc95xx_eth_send,
  869. .recv = smsc95xx_eth_recv,
  870. .free_pkt = smsc95xx_free_pkt,
  871. .stop = smsc95xx_eth_stop,
  872. .write_hwaddr = smsc95xx_write_hwaddr,
  873. };
  874. U_BOOT_DRIVER(smsc95xx_eth) = {
  875. .name = "smsc95xx_eth",
  876. .id = UCLASS_ETH,
  877. .probe = smsc95xx_eth_probe,
  878. .ops = &smsc95xx_eth_ops,
  879. .priv_auto_alloc_size = sizeof(struct smsc95xx_private),
  880. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  881. };
  882. static const struct usb_device_id smsc95xx_eth_id_table[] = {
  883. { USB_DEVICE(0x05ac, 0x1402) },
  884. { USB_DEVICE(0x0424, 0xec00) }, /* LAN9512/LAN9514 Ethernet */
  885. { USB_DEVICE(0x0424, 0x9500) }, /* LAN9500 Ethernet */
  886. { USB_DEVICE(0x0424, 0x9730) }, /* LAN9730 Ethernet (HSIC) */
  887. { USB_DEVICE(0x0424, 0x9900) }, /* SMSC9500 USB Ethernet (SAL10) */
  888. { USB_DEVICE(0x0424, 0x9e00) }, /* LAN9500A Ethernet */
  889. { } /* Terminating entry */
  890. };
  891. U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table);
  892. #endif