ehci-sunxi.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Sunxi ehci glue
  4. *
  5. * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
  6. * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
  7. *
  8. * Based on code from
  9. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  10. */
  11. #include <common.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/io.h>
  14. #include <dm.h>
  15. #include "ehci.h"
  16. #include <generic-phy.h>
  17. #ifdef CONFIG_SUNXI_GEN_SUN4I
  18. #define AHB_CLK_DIST 2
  19. #else
  20. #define AHB_CLK_DIST 1
  21. #endif
  22. #define SUN6I_AHB_RESET0_CFG_OFFSET 0x2c0
  23. #define SUN9I_AHB_RESET0_CFG_OFFSET 0x5a0
  24. struct ehci_sunxi_cfg {
  25. bool has_reset;
  26. u32 extra_ahb_gate_mask;
  27. u32 reset0_cfg_offset;
  28. };
  29. struct ehci_sunxi_priv {
  30. struct ehci_ctrl ehci;
  31. struct sunxi_ccm_reg *ccm;
  32. u32 *reset0_cfg;
  33. int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
  34. struct phy phy;
  35. const struct ehci_sunxi_cfg *cfg;
  36. };
  37. static int ehci_usb_probe(struct udevice *dev)
  38. {
  39. struct usb_platdata *plat = dev_get_platdata(dev);
  40. struct ehci_sunxi_priv *priv = dev_get_priv(dev);
  41. struct ehci_hccr *hccr = (struct ehci_hccr *)devfdt_get_addr(dev);
  42. struct ehci_hcor *hcor;
  43. int extra_ahb_gate_mask = 0;
  44. int phys, ret;
  45. priv->cfg = (const struct ehci_sunxi_cfg *)dev_get_driver_data(dev);
  46. priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  47. if (IS_ERR(priv->ccm))
  48. return PTR_ERR(priv->ccm);
  49. priv->reset0_cfg = (void *)priv->ccm +
  50. priv->cfg->reset0_cfg_offset;
  51. phys = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
  52. if (phys < 0) {
  53. phys = 0;
  54. goto no_phy;
  55. }
  56. ret = generic_phy_get_by_name(dev, "usb", &priv->phy);
  57. if (ret) {
  58. pr_err("failed to get %s usb PHY\n", dev->name);
  59. return ret;
  60. }
  61. ret = generic_phy_init(&priv->phy);
  62. if (ret) {
  63. pr_err("failed to init %s USB PHY\n", dev->name);
  64. return ret;
  65. }
  66. ret = generic_phy_power_on(&priv->phy);
  67. if (ret) {
  68. pr_err("failed to power on %s USB PHY\n", dev->name);
  69. return ret;
  70. }
  71. no_phy:
  72. /*
  73. * This should go away once we've moved to the driver model for
  74. * clocks resp. phys.
  75. */
  76. priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
  77. extra_ahb_gate_mask = priv->cfg->extra_ahb_gate_mask;
  78. priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
  79. extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
  80. setbits_le32(&priv->ccm->ahb_gate0,
  81. priv->ahb_gate_mask | extra_ahb_gate_mask);
  82. if (priv->cfg->has_reset)
  83. setbits_le32(priv->reset0_cfg,
  84. priv->ahb_gate_mask | extra_ahb_gate_mask);
  85. hcor = (struct ehci_hcor *)((uintptr_t)hccr +
  86. HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
  87. return ehci_register(dev, hccr, hcor, NULL, 0, plat->init_type);
  88. }
  89. static int ehci_usb_remove(struct udevice *dev)
  90. {
  91. struct ehci_sunxi_priv *priv = dev_get_priv(dev);
  92. int ret;
  93. if (generic_phy_valid(&priv->phy)) {
  94. ret = generic_phy_exit(&priv->phy);
  95. if (ret) {
  96. pr_err("failed to exit %s USB PHY\n", dev->name);
  97. return ret;
  98. }
  99. }
  100. ret = ehci_deregister(dev);
  101. if (ret)
  102. return ret;
  103. if (priv->cfg->has_reset)
  104. clrbits_le32(priv->reset0_cfg, priv->ahb_gate_mask);
  105. clrbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask);
  106. return 0;
  107. }
  108. static const struct ehci_sunxi_cfg sun4i_a10_cfg = {
  109. .has_reset = false,
  110. };
  111. static const struct ehci_sunxi_cfg sun6i_a31_cfg = {
  112. .has_reset = true,
  113. .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET,
  114. };
  115. static const struct ehci_sunxi_cfg sun8i_h3_cfg = {
  116. .has_reset = true,
  117. .extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0,
  118. .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET,
  119. };
  120. static const struct ehci_sunxi_cfg sun9i_a80_cfg = {
  121. .has_reset = true,
  122. .reset0_cfg_offset = SUN9I_AHB_RESET0_CFG_OFFSET,
  123. };
  124. static const struct udevice_id ehci_usb_ids[] = {
  125. {
  126. .compatible = "allwinner,sun4i-a10-ehci",
  127. .data = (ulong)&sun4i_a10_cfg,
  128. },
  129. {
  130. .compatible = "allwinner,sun5i-a13-ehci",
  131. .data = (ulong)&sun4i_a10_cfg,
  132. },
  133. {
  134. .compatible = "allwinner,sun6i-a31-ehci",
  135. .data = (ulong)&sun6i_a31_cfg,
  136. },
  137. {
  138. .compatible = "allwinner,sun7i-a20-ehci",
  139. .data = (ulong)&sun4i_a10_cfg,
  140. },
  141. {
  142. .compatible = "allwinner,sun8i-a23-ehci",
  143. .data = (ulong)&sun6i_a31_cfg,
  144. },
  145. {
  146. .compatible = "allwinner,sun8i-a83t-ehci",
  147. .data = (ulong)&sun6i_a31_cfg,
  148. },
  149. {
  150. .compatible = "allwinner,sun8i-h3-ehci",
  151. .data = (ulong)&sun8i_h3_cfg,
  152. },
  153. {
  154. .compatible = "allwinner,sun9i-a80-ehci",
  155. .data = (ulong)&sun9i_a80_cfg,
  156. },
  157. {
  158. .compatible = "allwinner,sun50i-a64-ehci",
  159. .data = (ulong)&sun8i_h3_cfg,
  160. },
  161. { /* sentinel */ }
  162. };
  163. U_BOOT_DRIVER(ehci_sunxi) = {
  164. .name = "ehci_sunxi",
  165. .id = UCLASS_USB,
  166. .of_match = ehci_usb_ids,
  167. .probe = ehci_usb_probe,
  168. .remove = ehci_usb_remove,
  169. .ops = &ehci_usb_ops,
  170. .platdata_auto_alloc_size = sizeof(struct usb_platdata),
  171. .priv_auto_alloc_size = sizeof(struct ehci_sunxi_priv),
  172. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  173. };