ddr.h 3.5 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __DDR_H__
  7. #define __DDR_H__
  8. struct board_specific_parameters {
  9. u32 n_ranks;
  10. u32 datarate_mhz_high;
  11. u32 rank_gb;
  12. u32 clk_adjust;
  13. u32 wrlvl_start;
  14. u32 wrlvl_ctl_2;
  15. u32 wrlvl_ctl_3;
  16. u32 cpo;
  17. u32 write_data_delay;
  18. u32 force_2T;
  19. };
  20. /*
  21. * These tables contain all valid speeds we want to override with board
  22. * specific parameters. datarate_mhz_high values need to be in ascending order
  23. * for each n_ranks group.
  24. */
  25. #ifdef CONFIG_T4240QDS
  26. static const struct board_specific_parameters udimm0[] = {
  27. /*
  28. * memory controller 0
  29. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
  30. * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
  31. */
  32. {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
  33. {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
  34. {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
  35. {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
  36. {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
  37. {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
  38. {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
  39. {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
  40. {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
  41. {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
  42. {}
  43. };
  44. static const struct board_specific_parameters rdimm0[] = {
  45. /*
  46. * memory controller 0
  47. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
  48. * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
  49. */
  50. {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
  51. {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
  52. {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
  53. {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
  54. {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
  55. {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
  56. {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
  57. {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
  58. {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
  59. {}
  60. };
  61. #else /* CONFIG_T4240EMU */
  62. static const struct board_specific_parameters udimm0[] = {
  63. /*
  64. * memory controller 0
  65. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
  66. * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
  67. */
  68. {2, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
  69. {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
  70. {}
  71. };
  72. static const struct board_specific_parameters rdimm0[] = {
  73. /*
  74. * memory controller 0
  75. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
  76. * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
  77. */
  78. {4, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0},
  79. {2, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0},
  80. {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
  81. {}
  82. };
  83. #endif /* CONFIG_T4240EMU */
  84. /*
  85. * The three slots have slightly different timing. The center values are good
  86. * for all slots. We use identical speed tables for them. In future use, if
  87. * DIMMs require separated tables, make more entries as needed.
  88. */
  89. static const struct board_specific_parameters *udimms[] = {
  90. udimm0,
  91. };
  92. /*
  93. * The three slots have slightly different timing. See comments above.
  94. */
  95. static const struct board_specific_parameters *rdimms[] = {
  96. rdimm0,
  97. };
  98. #endif