ddr.c 3.3 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * Version 2 or later as published by the Free Software Foundation.
  7. */
  8. #include <common.h>
  9. #include <i2c.h>
  10. #include <hwconfig.h>
  11. #include <asm/mmu.h>
  12. #include <asm/fsl_ddr_sdram.h>
  13. #include <asm/fsl_ddr_dimm_params.h>
  14. #include <asm/fsl_law.h>
  15. #include "ddr.h"
  16. DECLARE_GLOBAL_DATA_PTR;
  17. void fsl_ddr_board_options(memctl_options_t *popts,
  18. dimm_params_t *pdimm,
  19. unsigned int ctrl_num)
  20. {
  21. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  22. ulong ddr_freq;
  23. if (ctrl_num > 2) {
  24. printf("Not supported controller number %d\n", ctrl_num);
  25. return;
  26. }
  27. if (!pdimm->n_ranks)
  28. return;
  29. /*
  30. * we use identical timing for all slots. If needed, change the code
  31. * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  32. */
  33. if (popts->registered_dimm_en)
  34. pbsp = rdimms[0];
  35. else
  36. pbsp = udimms[0];
  37. /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  38. * freqency and n_banks specified in board_specific_parameters table.
  39. */
  40. ddr_freq = get_ddr_freq(0) / 1000000;
  41. while (pbsp->datarate_mhz_high) {
  42. if (pbsp->n_ranks == pdimm->n_ranks &&
  43. (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  44. if (ddr_freq <= pbsp->datarate_mhz_high) {
  45. popts->cpo_override = pbsp->cpo;
  46. popts->write_data_delay =
  47. pbsp->write_data_delay;
  48. popts->clk_adjust = pbsp->clk_adjust;
  49. popts->wrlvl_start = pbsp->wrlvl_start;
  50. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  51. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  52. popts->twoT_en = pbsp->force_2T;
  53. goto found;
  54. }
  55. pbsp_highest = pbsp;
  56. }
  57. pbsp++;
  58. }
  59. if (pbsp_highest) {
  60. printf("Error: board specific timing not found "
  61. "for data rate %lu MT/s\n"
  62. "Trying to use the highest speed (%u) parameters\n",
  63. ddr_freq, pbsp_highest->datarate_mhz_high);
  64. popts->cpo_override = pbsp_highest->cpo;
  65. popts->write_data_delay = pbsp_highest->write_data_delay;
  66. popts->clk_adjust = pbsp_highest->clk_adjust;
  67. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  68. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  69. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  70. popts->twoT_en = pbsp_highest->force_2T;
  71. } else {
  72. panic("DIMM is not supported by this board");
  73. }
  74. found:
  75. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  76. "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  77. "wrlvl_ctrl_3 0x%x\n",
  78. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  79. pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  80. pbsp->wrlvl_ctl_3);
  81. /*
  82. * Factors to consider for half-strength driver enable:
  83. * - number of DIMMs installed
  84. */
  85. popts->half_strength_driver_enable = 0;
  86. /*
  87. * Write leveling override
  88. */
  89. popts->wrlvl_override = 1;
  90. popts->wrlvl_sample = 0xf;
  91. /*
  92. * Rtt and Rtt_WR override
  93. */
  94. popts->rtt_override = 0;
  95. /* Enable ZQ calibration */
  96. popts->zq_en = 1;
  97. /* DHC_EN =1, ODT = 75 Ohm */
  98. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  99. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  100. }
  101. phys_size_t initdram(int board_type)
  102. {
  103. phys_size_t dram_size;
  104. puts("Initializing....using SPD\n");
  105. dram_size = fsl_ddr_sdram();
  106. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  107. dram_size *= 0x100000;
  108. puts(" DDR: ");
  109. return dram_size;
  110. }