main.c 21 KB

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  1. /*
  2. * Copyright 2008-2012 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * Version 2 as published by the Free Software Foundation.
  7. */
  8. /*
  9. * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  10. * Based on code from spd_sdram.c
  11. * Author: James Yang [at freescale.com]
  12. */
  13. #include <common.h>
  14. #include <i2c.h>
  15. #include <asm/fsl_ddr_sdram.h>
  16. #include <asm/fsl_law.h>
  17. #include "ddr.h"
  18. void fsl_ddr_set_lawbar(
  19. const common_timing_params_t *memctl_common_params,
  20. unsigned int memctl_interleaved,
  21. unsigned int ctrl_num);
  22. void fsl_ddr_set_intl3r(const unsigned int granule_size);
  23. #if defined(SPD_EEPROM_ADDRESS) || \
  24. defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
  25. defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
  26. #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  27. u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  28. [0][0] = SPD_EEPROM_ADDRESS,
  29. };
  30. #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  31. u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  32. [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
  33. [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
  34. };
  35. #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  36. u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  37. [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
  38. [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
  39. };
  40. #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  41. u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  42. [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
  43. [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
  44. [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
  45. [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
  46. };
  47. #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  48. u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  49. [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
  50. [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
  51. [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
  52. };
  53. #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  54. u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  55. [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
  56. [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
  57. [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
  58. [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
  59. [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */
  60. [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */
  61. };
  62. #endif
  63. static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  64. {
  65. int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
  66. sizeof(generic_spd_eeprom_t));
  67. if (ret) {
  68. if (i2c_address ==
  69. #ifdef SPD_EEPROM_ADDRESS
  70. SPD_EEPROM_ADDRESS
  71. #elif defined(SPD_EEPROM_ADDRESS1)
  72. SPD_EEPROM_ADDRESS1
  73. #endif
  74. ) {
  75. printf("DDR: failed to read SPD from address %u\n",
  76. i2c_address);
  77. } else {
  78. debug("DDR: failed to read SPD from address %u\n",
  79. i2c_address);
  80. }
  81. memset(spd, 0, sizeof(generic_spd_eeprom_t));
  82. }
  83. }
  84. __attribute__((weak, alias("__get_spd")))
  85. void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
  86. void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  87. unsigned int ctrl_num)
  88. {
  89. unsigned int i;
  90. unsigned int i2c_address = 0;
  91. if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
  92. printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  93. return;
  94. }
  95. for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  96. i2c_address = spd_i2c_addr[ctrl_num][i];
  97. get_spd(&(ctrl_dimms_spd[i]), i2c_address);
  98. }
  99. }
  100. #else
  101. void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  102. unsigned int ctrl_num)
  103. {
  104. }
  105. #endif /* SPD_EEPROM_ADDRESSx */
  106. /*
  107. * ASSUMPTIONS:
  108. * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
  109. * - Same memory data bus width on all controllers
  110. *
  111. * NOTES:
  112. *
  113. * The memory controller and associated documentation use confusing
  114. * terminology when referring to the orgranization of DRAM.
  115. *
  116. * Here is a terminology translation table:
  117. *
  118. * memory controller/documention |industry |this code |signals
  119. * -------------------------------|-----------|-----------|-----------------
  120. * physical bank/bank |rank |rank |chip select (CS)
  121. * logical bank/sub-bank |bank |bank |bank address (BA)
  122. * page/row |row |page |row address
  123. * ??? |column |column |column address
  124. *
  125. * The naming confusion is further exacerbated by the descriptions of the
  126. * memory controller interleaving feature, where accesses are interleaved
  127. * _BETWEEN_ two seperate memory controllers. This is configured only in
  128. * CS0_CONFIG[INTLV_CTL] of each memory controller.
  129. *
  130. * memory controller documentation | number of chip selects
  131. * | per memory controller supported
  132. * --------------------------------|-----------------------------------------
  133. * cache line interleaving | 1 (CS0 only)
  134. * page interleaving | 1 (CS0 only)
  135. * bank interleaving | 1 (CS0 only)
  136. * superbank interleraving | depends on bank (chip select)
  137. * | interleraving [rank interleaving]
  138. * | mode used on every memory controller
  139. *
  140. * Even further confusing is the existence of the interleaving feature
  141. * _WITHIN_ each memory controller. The feature is referred to in
  142. * documentation as chip select interleaving or bank interleaving,
  143. * although it is configured in the DDR_SDRAM_CFG field.
  144. *
  145. * Name of field | documentation name | this code
  146. * -----------------------------|-----------------------|------------------
  147. * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
  148. * | interleaving
  149. */
  150. const char *step_string_tbl[] = {
  151. "STEP_GET_SPD",
  152. "STEP_COMPUTE_DIMM_PARMS",
  153. "STEP_COMPUTE_COMMON_PARMS",
  154. "STEP_GATHER_OPTS",
  155. "STEP_ASSIGN_ADDRESSES",
  156. "STEP_COMPUTE_REGS",
  157. "STEP_PROGRAM_REGS",
  158. "STEP_ALL"
  159. };
  160. const char * step_to_string(unsigned int step) {
  161. unsigned int s = __ilog2(step);
  162. if ((1 << s) != step)
  163. return step_string_tbl[7];
  164. return step_string_tbl[s];
  165. }
  166. static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
  167. unsigned int dbw_cap_adj[])
  168. {
  169. int i, j;
  170. unsigned long long total_mem, current_mem_base, total_ctlr_mem;
  171. unsigned long long rank_density, ctlr_density = 0;
  172. /*
  173. * If a reduced data width is requested, but the SPD
  174. * specifies a physically wider device, adjust the
  175. * computed dimm capacities accordingly before
  176. * assigning addresses.
  177. */
  178. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  179. unsigned int found = 0;
  180. switch (pinfo->memctl_opts[i].data_bus_width) {
  181. case 2:
  182. /* 16-bit */
  183. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  184. unsigned int dw;
  185. if (!pinfo->dimm_params[i][j].n_ranks)
  186. continue;
  187. dw = pinfo->dimm_params[i][j].primary_sdram_width;
  188. if ((dw == 72 || dw == 64)) {
  189. dbw_cap_adj[i] = 2;
  190. break;
  191. } else if ((dw == 40 || dw == 32)) {
  192. dbw_cap_adj[i] = 1;
  193. break;
  194. }
  195. }
  196. break;
  197. case 1:
  198. /* 32-bit */
  199. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  200. unsigned int dw;
  201. dw = pinfo->dimm_params[i][j].data_width;
  202. if (pinfo->dimm_params[i][j].n_ranks
  203. && (dw == 72 || dw == 64)) {
  204. /*
  205. * FIXME: can't really do it
  206. * like this because this just
  207. * further reduces the memory
  208. */
  209. found = 1;
  210. break;
  211. }
  212. }
  213. if (found) {
  214. dbw_cap_adj[i] = 1;
  215. }
  216. break;
  217. case 0:
  218. /* 64-bit */
  219. break;
  220. default:
  221. printf("unexpected data bus width "
  222. "specified controller %u\n", i);
  223. return 1;
  224. }
  225. debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
  226. }
  227. current_mem_base = 0ull;
  228. total_mem = 0;
  229. if (pinfo->memctl_opts[0].memctl_interleaving) {
  230. rank_density = pinfo->dimm_params[0][0].rank_density >>
  231. dbw_cap_adj[0];
  232. switch (pinfo->memctl_opts[0].ba_intlv_ctl &
  233. FSL_DDR_CS0_CS1_CS2_CS3) {
  234. case FSL_DDR_CS0_CS1_CS2_CS3:
  235. ctlr_density = 4 * rank_density;
  236. break;
  237. case FSL_DDR_CS0_CS1:
  238. case FSL_DDR_CS0_CS1_AND_CS2_CS3:
  239. ctlr_density = 2 * rank_density;
  240. break;
  241. case FSL_DDR_CS2_CS3:
  242. default:
  243. ctlr_density = rank_density;
  244. break;
  245. }
  246. debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
  247. rank_density, ctlr_density);
  248. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  249. if (pinfo->memctl_opts[i].memctl_interleaving) {
  250. switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
  251. case FSL_DDR_CACHE_LINE_INTERLEAVING:
  252. case FSL_DDR_PAGE_INTERLEAVING:
  253. case FSL_DDR_BANK_INTERLEAVING:
  254. case FSL_DDR_SUPERBANK_INTERLEAVING:
  255. total_ctlr_mem = 2 * ctlr_density;
  256. break;
  257. case FSL_DDR_3WAY_1KB_INTERLEAVING:
  258. case FSL_DDR_3WAY_4KB_INTERLEAVING:
  259. case FSL_DDR_3WAY_8KB_INTERLEAVING:
  260. total_ctlr_mem = 3 * ctlr_density;
  261. break;
  262. case FSL_DDR_4WAY_1KB_INTERLEAVING:
  263. case FSL_DDR_4WAY_4KB_INTERLEAVING:
  264. case FSL_DDR_4WAY_8KB_INTERLEAVING:
  265. total_ctlr_mem = 4 * ctlr_density;
  266. break;
  267. default:
  268. panic("Unknown interleaving mode");
  269. }
  270. pinfo->common_timing_params[i].base_address =
  271. current_mem_base;
  272. pinfo->common_timing_params[i].total_mem =
  273. total_ctlr_mem;
  274. total_mem = current_mem_base + total_ctlr_mem;
  275. debug("ctrl %d base 0x%llx\n", i, current_mem_base);
  276. debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
  277. } else {
  278. /* when 3rd controller not interleaved */
  279. current_mem_base = total_mem;
  280. total_ctlr_mem = 0;
  281. pinfo->common_timing_params[i].base_address =
  282. current_mem_base;
  283. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  284. unsigned long long cap =
  285. pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
  286. pinfo->dimm_params[i][j].base_address =
  287. current_mem_base;
  288. debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
  289. current_mem_base += cap;
  290. total_ctlr_mem += cap;
  291. }
  292. debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
  293. pinfo->common_timing_params[i].total_mem =
  294. total_ctlr_mem;
  295. total_mem += total_ctlr_mem;
  296. }
  297. }
  298. } else {
  299. /*
  300. * Simple linear assignment if memory
  301. * controllers are not interleaved.
  302. */
  303. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  304. total_ctlr_mem = 0;
  305. pinfo->common_timing_params[i].base_address =
  306. current_mem_base;
  307. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  308. /* Compute DIMM base addresses. */
  309. unsigned long long cap =
  310. pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
  311. pinfo->dimm_params[i][j].base_address =
  312. current_mem_base;
  313. debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
  314. current_mem_base += cap;
  315. total_ctlr_mem += cap;
  316. }
  317. debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
  318. pinfo->common_timing_params[i].total_mem =
  319. total_ctlr_mem;
  320. total_mem += total_ctlr_mem;
  321. }
  322. }
  323. debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
  324. return total_mem;
  325. }
  326. /* Use weak function to allow board file to override the address assignment */
  327. __attribute__((weak, alias("__step_assign_addresses")))
  328. unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
  329. unsigned int dbw_cap_adj[]);
  330. unsigned long long
  331. fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
  332. unsigned int size_only)
  333. {
  334. unsigned int i, j;
  335. unsigned long long total_mem = 0;
  336. int assert_reset;
  337. fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
  338. common_timing_params_t *timing_params = pinfo->common_timing_params;
  339. assert_reset = board_need_mem_reset();
  340. /* data bus width capacity adjust shift amount */
  341. unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
  342. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  343. dbw_capacity_adjust[i] = 0;
  344. }
  345. debug("starting at step %u (%s)\n",
  346. start_step, step_to_string(start_step));
  347. switch (start_step) {
  348. case STEP_GET_SPD:
  349. #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
  350. /* STEP 1: Gather all DIMM SPD data */
  351. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  352. fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
  353. }
  354. case STEP_COMPUTE_DIMM_PARMS:
  355. /* STEP 2: Compute DIMM parameters from SPD data */
  356. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  357. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  358. unsigned int retval;
  359. generic_spd_eeprom_t *spd =
  360. &(pinfo->spd_installed_dimms[i][j]);
  361. dimm_params_t *pdimm =
  362. &(pinfo->dimm_params[i][j]);
  363. retval = compute_dimm_parameters(spd, pdimm, i);
  364. #ifdef CONFIG_SYS_DDR_RAW_TIMING
  365. if (!i && !j && retval) {
  366. printf("SPD error on controller %d! "
  367. "Trying fallback to raw timing "
  368. "calculation\n", i);
  369. fsl_ddr_get_dimm_params(pdimm, i, j);
  370. }
  371. #else
  372. if (retval == 2) {
  373. printf("Error: compute_dimm_parameters"
  374. " non-zero returned FATAL value "
  375. "for memctl=%u dimm=%u\n", i, j);
  376. return 0;
  377. }
  378. #endif
  379. if (retval) {
  380. debug("Warning: compute_dimm_parameters"
  381. " non-zero return value for memctl=%u "
  382. "dimm=%u\n", i, j);
  383. }
  384. }
  385. }
  386. #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
  387. case STEP_COMPUTE_DIMM_PARMS:
  388. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  389. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  390. dimm_params_t *pdimm =
  391. &(pinfo->dimm_params[i][j]);
  392. fsl_ddr_get_dimm_params(pdimm, i, j);
  393. }
  394. }
  395. debug("Filling dimm parameters from board specific file\n");
  396. #endif
  397. case STEP_COMPUTE_COMMON_PARMS:
  398. /*
  399. * STEP 3: Compute a common set of timing parameters
  400. * suitable for all of the DIMMs on each memory controller
  401. */
  402. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  403. debug("Computing lowest common DIMM"
  404. " parameters for memctl=%u\n", i);
  405. compute_lowest_common_dimm_parameters(
  406. pinfo->dimm_params[i],
  407. &timing_params[i],
  408. CONFIG_DIMM_SLOTS_PER_CTLR);
  409. }
  410. case STEP_GATHER_OPTS:
  411. /* STEP 4: Gather configuration requirements from user */
  412. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  413. debug("Reloading memory controller "
  414. "configuration options for memctl=%u\n", i);
  415. /*
  416. * This "reloads" the memory controller options
  417. * to defaults. If the user "edits" an option,
  418. * next_step points to the step after this,
  419. * which is currently STEP_ASSIGN_ADDRESSES.
  420. */
  421. populate_memctl_options(
  422. timing_params[i].all_DIMMs_registered,
  423. &pinfo->memctl_opts[i],
  424. pinfo->dimm_params[i], i);
  425. /*
  426. * For RDIMMs, JEDEC spec requires clocks to be stable
  427. * before reset signal is deasserted. For the boards
  428. * using fixed parameters, this function should be
  429. * be called from board init file.
  430. */
  431. if (timing_params[i].all_DIMMs_registered)
  432. assert_reset = 1;
  433. }
  434. if (assert_reset) {
  435. debug("Asserting mem reset\n");
  436. board_assert_mem_reset();
  437. }
  438. case STEP_ASSIGN_ADDRESSES:
  439. /* STEP 5: Assign addresses to chip selects */
  440. check_interleaving_options(pinfo);
  441. total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
  442. case STEP_COMPUTE_REGS:
  443. /* STEP 6: compute controller register values */
  444. debug("FSL Memory ctrl register computation\n");
  445. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  446. if (timing_params[i].ndimms_present == 0) {
  447. memset(&ddr_reg[i], 0,
  448. sizeof(fsl_ddr_cfg_regs_t));
  449. continue;
  450. }
  451. compute_fsl_memctl_config_regs(
  452. &pinfo->memctl_opts[i],
  453. &ddr_reg[i], &timing_params[i],
  454. pinfo->dimm_params[i],
  455. dbw_capacity_adjust[i],
  456. size_only);
  457. }
  458. default:
  459. break;
  460. }
  461. {
  462. /*
  463. * Compute the amount of memory available just by
  464. * looking for the highest valid CSn_BNDS value.
  465. * This allows us to also experiment with using
  466. * only CS0 when using dual-rank DIMMs.
  467. */
  468. unsigned int max_end = 0;
  469. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  470. for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
  471. fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
  472. if (reg->cs[j].config & 0x80000000) {
  473. unsigned int end;
  474. /*
  475. * 0xfffffff is a special value we put
  476. * for unused bnds
  477. */
  478. if (reg->cs[j].bnds == 0xffffffff)
  479. continue;
  480. end = reg->cs[j].bnds & 0xffff;
  481. if (end > max_end) {
  482. max_end = end;
  483. }
  484. }
  485. }
  486. }
  487. total_mem = 1 + (((unsigned long long)max_end << 24ULL)
  488. | 0xFFFFFFULL);
  489. }
  490. return total_mem;
  491. }
  492. /*
  493. * fsl_ddr_sdram() -- this is the main function to be called by
  494. * initdram() in the board file.
  495. *
  496. * It returns amount of memory configured in bytes.
  497. */
  498. phys_size_t fsl_ddr_sdram(void)
  499. {
  500. unsigned int i;
  501. unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
  502. unsigned long long total_memory;
  503. fsl_ddr_info_t info;
  504. int deassert_reset;
  505. /* Reset info structure. */
  506. memset(&info, 0, sizeof(fsl_ddr_info_t));
  507. /* Compute it once normally. */
  508. #ifdef CONFIG_FSL_DDR_INTERACTIVE
  509. if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */
  510. total_memory = fsl_ddr_interactive(&info, 0);
  511. } else if (fsl_ddr_interactive_env_var_exists()) {
  512. total_memory = fsl_ddr_interactive(&info, 1);
  513. } else
  514. #endif
  515. total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
  516. /* setup 3-way interleaving before enabling DDRC */
  517. if (info.memctl_opts[0].memctl_interleaving) {
  518. switch (info.memctl_opts[0].memctl_interleaving_mode) {
  519. case FSL_DDR_3WAY_1KB_INTERLEAVING:
  520. case FSL_DDR_3WAY_4KB_INTERLEAVING:
  521. case FSL_DDR_3WAY_8KB_INTERLEAVING:
  522. fsl_ddr_set_intl3r(
  523. info.memctl_opts[0].memctl_interleaving_mode);
  524. break;
  525. default:
  526. break;
  527. }
  528. }
  529. /*
  530. * Program configuration registers.
  531. * JEDEC specs requires clocks to be stable before deasserting reset
  532. * for RDIMMs. Clocks start after chip select is enabled and clock
  533. * control register is set. During step 1, all controllers have their
  534. * registers set but not enabled. Step 2 proceeds after deasserting
  535. * reset through board FPGA or GPIO.
  536. * For non-registered DIMMs, initialization can go through but it is
  537. * also OK to follow the same flow.
  538. */
  539. deassert_reset = board_need_mem_reset();
  540. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  541. if (info.common_timing_params[i].all_DIMMs_registered)
  542. deassert_reset = 1;
  543. }
  544. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  545. debug("Programming controller %u\n", i);
  546. if (info.common_timing_params[i].ndimms_present == 0) {
  547. debug("No dimms present on controller %u; "
  548. "skipping programming\n", i);
  549. continue;
  550. }
  551. /*
  552. * The following call with step = 1 returns before enabling
  553. * the controller. It has to finish with step = 2 later.
  554. */
  555. fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i,
  556. deassert_reset ? 1 : 0);
  557. }
  558. if (deassert_reset) {
  559. /* Use board FPGA or GPIO to deassert reset signal */
  560. debug("Deasserting mem reset\n");
  561. board_deassert_mem_reset();
  562. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  563. /* Call with step = 2 to continue initialization */
  564. fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]),
  565. i, 2);
  566. }
  567. }
  568. /* program LAWs */
  569. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  570. if (info.memctl_opts[i].memctl_interleaving) {
  571. switch (info.memctl_opts[i].memctl_interleaving_mode) {
  572. case FSL_DDR_CACHE_LINE_INTERLEAVING:
  573. case FSL_DDR_PAGE_INTERLEAVING:
  574. case FSL_DDR_BANK_INTERLEAVING:
  575. case FSL_DDR_SUPERBANK_INTERLEAVING:
  576. if (i == 0) {
  577. law_memctl = LAW_TRGT_IF_DDR_INTRLV;
  578. fsl_ddr_set_lawbar(&info.common_timing_params[i],
  579. law_memctl, i);
  580. } else if (i == 2) {
  581. law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
  582. fsl_ddr_set_lawbar(&info.common_timing_params[i],
  583. law_memctl, i);
  584. }
  585. break;
  586. case FSL_DDR_3WAY_1KB_INTERLEAVING:
  587. case FSL_DDR_3WAY_4KB_INTERLEAVING:
  588. case FSL_DDR_3WAY_8KB_INTERLEAVING:
  589. law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
  590. if (i == 0) {
  591. fsl_ddr_set_lawbar(&info.common_timing_params[i],
  592. law_memctl, i);
  593. }
  594. break;
  595. case FSL_DDR_4WAY_1KB_INTERLEAVING:
  596. case FSL_DDR_4WAY_4KB_INTERLEAVING:
  597. case FSL_DDR_4WAY_8KB_INTERLEAVING:
  598. law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
  599. if (i == 0)
  600. fsl_ddr_set_lawbar(&info.common_timing_params[i],
  601. law_memctl, i);
  602. /* place holder for future 4-way interleaving */
  603. break;
  604. default:
  605. break;
  606. }
  607. } else {
  608. switch (i) {
  609. case 0:
  610. law_memctl = LAW_TRGT_IF_DDR_1;
  611. break;
  612. case 1:
  613. law_memctl = LAW_TRGT_IF_DDR_2;
  614. break;
  615. case 2:
  616. law_memctl = LAW_TRGT_IF_DDR_3;
  617. break;
  618. case 3:
  619. law_memctl = LAW_TRGT_IF_DDR_4;
  620. break;
  621. default:
  622. break;
  623. }
  624. fsl_ddr_set_lawbar(&info.common_timing_params[i],
  625. law_memctl, i);
  626. }
  627. }
  628. debug("total_memory by %s = %llu\n", __func__, total_memory);
  629. #if !defined(CONFIG_PHYS_64BIT)
  630. /* Check for 4G or more. Bad. */
  631. if (total_memory >= (1ull << 32)) {
  632. printf("Detected %lld MB of memory\n", total_memory >> 20);
  633. printf(" This U-Boot only supports < 4G of DDR\n");
  634. printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
  635. printf(" "); /* re-align to match init_func_ram print */
  636. total_memory = CONFIG_MAX_MEM_MAPPED;
  637. }
  638. #endif
  639. return total_memory;
  640. }
  641. /*
  642. * fsl_ddr_sdram_size() - This function only returns the size of the total
  643. * memory without setting ddr control registers.
  644. */
  645. phys_size_t
  646. fsl_ddr_sdram_size(void)
  647. {
  648. fsl_ddr_info_t info;
  649. unsigned long long total_memory = 0;
  650. memset(&info, 0 , sizeof(fsl_ddr_info_t));
  651. /* Compute it once normally. */
  652. total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
  653. return total_memory;
  654. }