u-boot/drivers/ddr/altera/sequencer_auto.h

/*
 * Copyright Altera Corporation (C) 2012-2015
 *
 * SPDX-License-Identifier:    BSD-3-Clause
 */


#define RW_MGR_READ_B2B_WAIT2 0x6A
#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
#define RW_MGR_REFRESH_ALL 0x14
#define RW_MGR_ZQCL 0x06
#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
#define RW_MGR_MRS2_MIRR 0x0A
#define RW_MGR_INIT_RESET_0_CKE_0 0x6E
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
#define RW_MGR_ACTIVATE_1 0x0F
#define RW_MGR_MRS2 0x04
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
#define RW_MGR_MRS1 0x03
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define RW_MGR_IDLE_LOOP1 0x7A
#else
#define RW_MGR_IDLE_LOOP1 0x7C
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
#define RW_MGR_MRS3 0x05
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define RW_MGR_IDLE_LOOP2 0x79
#else
#define RW_MGR_IDLE_LOOP2 0x7B
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define RW_MGR_RDIMM_CMD 0x78
#else
#define RW_MGR_RDIMM_CMD 0x7A
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
#define RW_MGR_GUARANTEED_READ_CONT 0x53
#define RW_MGR_MRS3_MIRR 0x0B
#define RW_MGR_IDLE 0x00
#define RW_MGR_READ_B2B 0x58
#define RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
#define RW_MGR_GUARANTEED_WRITE 0x17
#define RW_MGR_PRECHARGE_ALL 0x12
#define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define RW_MGR_SGLE_READ 0x7C
#else
#define RW_MGR_SGLE_READ 0x7E
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_MRS0_USER_MIRR 0x0C
#define RW_MGR_RETURN 0x01
#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
#define RW_MGR_MRS0_USER 0x07
#define RW_MGR_GUARANTEED_READ 0x4B
#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
#define RW_MGR_INIT_RESET_1_CKE_0 0x73
#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
#define RW_MGR_MRS0_DLL_RESET 0x02
#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
#define RW_MGR_LFSR_WR_RD_BANK_0 0x21
#define RW_MGR_CLEAR_DQS_ENABLE 0x48
#define RW_MGR_MRS1_MIRR 0x09
#define RW_MGR_READ_B2B_WAIT1 0x60
#define RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
#define RW_MGR_CONTENT_REFRESH_ALL 0x000980
#define RW_MGR_CONTENT_ZQCL 0x008380
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00
#define RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800
#define RW_MGR_CONTENT_MRS2_MIRR 0x008580
#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680
#define RW_MGR_CONTENT_ACTIVATE_1 0x000880
#define RW_MGR_CONTENT_MRS2 0x008280
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00
#define RW_MGR_CONTENT_MRS1 0x008200
#define RW_MGR_CONTENT_IDLE_LOOP1 0x00A680
#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8
#define RW_MGR_CONTENT_MRS3 0x008300
#define RW_MGR_CONTENT_IDLE_LOOP2 0x008680
#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0
#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88
#define RW_MGR_CONTENT_RDIMM_CMD 0x009180
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700
#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
#define RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
#define RW_MGR_CONTENT_MRS3_MIRR 0x008600
#define RW_MGR_CONTENT_IDLE 0x080000
#define RW_MGR_CONTENT_READ_B2B 0x040E88
#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
#define RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
#define RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080
#define RW_MGR_CONTENT_SGLE_READ 0x040F08
#define RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
#define RW_MGR_CONTENT_RETURN 0x080680
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80
#define RW_MGR_CONTENT_MRS0_USER 0x008100
#define RW_MGR_CONTENT_GUARANTEED_READ 0x001168
#define RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480
#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080
#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00
#define RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180
#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80
#define RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
#define RW_MGR_CONTENT_MRS1_MIRR 0x008500
#define RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680