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arch-pxa
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regs-uart.h

regs-uart.h 1.9 KB
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  1. /*
    2. 

  2.  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier:	GPL-2.0+
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef	__REGS_UART_H__
    8. 

  8. #define	__REGS_UART_H__
    9. 

  9. 

  10. #define	FFUART_BASE		0x40100000
    11. 

  11. #define	BTUART_BASE		0x40200000
    12. 

  12. #define	STUART_BASE		0x40700000
    13. 

  13. #define	HWUART_BASE		0x41600000
    14. 

  14. 

  15. struct pxa_uart_regs {
    16. 

  16. 	union {
    17. 

  17. 		uint32_t	thr;
    18. 

  18. 		uint32_t	rbr;
    19. 

  19. 		uint32_t	dll;
    20. 

  20. 	};
    21. 

  21. 	union {
    22. 

  22. 		uint32_t	ier;
    23. 

  23. 		uint32_t	dlh;
    24. 

  24. 	};
    25. 

  25. 	union {
    26. 

  26. 		uint32_t	fcr;
    27. 

  27. 		uint32_t	iir;
    28. 

  28. 	};
    29. 

  29. 	uint32_t	lcr;
    30. 

  30. 	uint32_t	mcr;
    31. 

  31. 	uint32_t	lsr;
    32. 

  32. 	uint32_t	msr;
    33. 

  33. 	uint32_t	spr;
    34. 

  34. 	uint32_t	isr;
    35. 

  35. };
    36. 

  36. 

  37. #define	IER_DMAE	(1 << 7)
    38. 

  38. #define	IER_UUE		(1 << 6)
    39. 

  39. #define	IER_NRZE	(1 << 5)
    40. 

  40. #define	IER_RTIOE	(1 << 4)
    41. 

  41. #define	IER_MIE		(1 << 3)
    42. 

  42. #define	IER_RLSE	(1 << 2)
    43. 

  43. #define	IER_TIE		(1 << 1)
    44. 

  44. #define	IER_RAVIE	(1 << 0)
    45. 

  45. 

  46. #define	IIR_FIFOES1	(1 << 7)
    47. 

  47. #define	IIR_FIFOES0	(1 << 6)
    48. 

  48. #define	IIR_TOD		(1 << 3)
    49. 

  49. #define	IIR_IID2	(1 << 2)
    50. 

  50. #define	IIR_IID1	(1 << 1)
    51. 

  51. #define	IIR_IP		(1 << 0)
    52. 

  52. 

  53. #define	FCR_ITL2	(1 << 7)
    54. 

  54. #define	FCR_ITL1	(1 << 6)
    55. 

  55. #define	FCR_RESETTF	(1 << 2)
    56. 

  56. #define	FCR_RESETRF	(1 << 1)
    57. 

  57. #define	FCR_TRFIFOE	(1 << 0)
    58. 

  58. #define	FCR_ITL_1	0
    59. 

  59. #define	FCR_ITL_8	(FCR_ITL1)
    60. 

  60. #define	FCR_ITL_16	(FCR_ITL2)
    61. 

  61. #define	FCR_ITL_32	(FCR_ITL2|FCR_ITL1)
    62. 

  62. 

  63. #define	LCR_DLAB	(1 << 7)
    64. 

  64. #define	LCR_SB		(1 << 6)
    65. 

  65. #define	LCR_STKYP	(1 << 5)
    66. 

  66. #define	LCR_EPS		(1 << 4)
    67. 

  67. #define	LCR_PEN		(1 << 3)
    68. 

  68. #define	LCR_STB		(1 << 2)
    69. 

  69. #define	LCR_WLS1	(1 << 1)
    70. 

  70. #define	LCR_WLS0	(1 << 0)
    71. 

  71. 

  72. #define	LSR_FIFOE	(1 << 7)
    73. 

  73. #define	LSR_TEMT	(1 << 6)
    74. 

  74. #define	LSR_TDRQ	(1 << 5)
    75. 

  75. #define	LSR_BI		(1 << 4)
    76. 

  76. #define	LSR_FE		(1 << 3)
    77. 

  77. #define	LSR_PE		(1 << 2)
    78. 

  78. #define	LSR_OE		(1 << 1)
    79. 

  79. #define	LSR_DR		(1 << 0)
    80. 

  80. 

  81. #define	MCR_LOOP	(1 << 4)
    82. 

  82. #define	MCR_OUT2	(1 << 3)
    83. 

  83. #define	MCR_OUT1	(1 << 2)
    84. 

  84. #define	MCR_RTS		(1 << 1)
    85. 

  85. #define	MCR_DTR		(1 << 0)
    86. 

  86. 

  87. #define	MSR_DCD		(1 << 7)
    88. 

  88. #define	MSR_RI		(1 << 6)
    89. 

  89. #define	MSR_DSR		(1 << 5)
    90. 

  90. #define	MSR_CTS		(1 << 4)
    91. 

  91. #define	MSR_DDCD	(1 << 3)
    92. 

  92. #define	MSR_TERI	(1 << 2)
    93. 

  93. #define	MSR_DDSR	(1 << 1)
    94. 

  94. #define	MSR_DCTS	(1 << 0)
    95. 

  95. 

  96. #endif	/* __REGS_UART_H__ */
    97.