mx6_plugin.S 4.2 KB

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  1. /*
  2. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <config.h>
  7. #ifdef CONFIG_ROM_UNIFIED_SECTIONS
  8. #define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
  9. #define ROM_VERSION_OFFSET 0x80
  10. #else
  11. #define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0
  12. #define ROM_VERSION_OFFSET 0x48
  13. #endif
  14. #define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 0xC4
  15. #define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 0xC4
  16. #define ROM_API_HWCNFG_SETUP_OFFSET 0x08
  17. #define ROM_VERSION_TO10 0x10
  18. #define ROM_VERSION_TO12 0x12
  19. #define ROM_VERSION_TO15 0x15
  20. plugin_start:
  21. push {r0-r4, lr}
  22. imx6_ddr_setting
  23. imx6_clock_gating
  24. imx6_qos_setting
  25. /*
  26. * The following is to fill in those arguments for this ROM function
  27. * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
  28. * This function is used to copy data from the storage media into DDR.
  29. * start - Initial (possibly partial) image load address on entry.
  30. * Final image load address on exit.
  31. * bytes - Initial (possibly partial) image size on entry.
  32. * Final image size on exit.
  33. * boot_data - Initial @ref ivt Boot Data load address.
  34. */
  35. adr r0, boot_data2
  36. adr r1, image_len2
  37. adr r2, boot_data2
  38. #ifdef CONFIG_NOR_BOOT
  39. #ifdef CONFIG_MX6SX
  40. ldr r3, =ROM_VERSION_OFFSET
  41. ldr r4, [r3]
  42. cmp r4, #ROM_VERSION_TO10
  43. bgt before_calling_rom___pu_irom_hwcnfg_setup
  44. ldr r3, =0x00900b00
  45. ldr r4, =0x50000000
  46. str r4, [r3, #0x5c]
  47. #else
  48. ldr r3, =0x00900800
  49. ldr r4, =0x08000000
  50. str r4, [r3, #0xc0]
  51. #endif
  52. #endif
  53. /*
  54. * check the _pu_irom_api_table for the address
  55. */
  56. before_calling_rom___pu_irom_hwcnfg_setup:
  57. ldr r3, =ROM_VERSION_OFFSET
  58. ldr r4, [r3]
  59. #if defined(CONFIG_MX6SOLO) || defined(CONFIG_MX6DL)
  60. ldr r3, =ROM_VERSION_TO12
  61. cmp r4, r3
  62. ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12
  63. ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
  64. #elif defined(CONFIG_MX6Q)
  65. ldr r3, =ROM_VERSION_TO15
  66. cmp r4, r3
  67. ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15
  68. ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
  69. #else
  70. ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
  71. #endif
  72. ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
  73. blx r4
  74. after_calling_rom___pu_irom_hwcnfg_setup:
  75. /*
  76. * ROM_API_HWCNFG_SETUP function enables MMU & Caches.
  77. * Thus disable MMU & Caches.
  78. */
  79. mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0*/
  80. ands r0, r0, #0x1 /* check if MMU is enabled */
  81. beq mmu_disable_notreq /* exit if MMU is already disabled */
  82. /* Disable caches, MMU */
  83. mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0 */
  84. bic r0, r0, #(1 << 2) /* disable D Cache */
  85. bic r0, r0, #0x1 /* clear bit 0 ; MMU off */
  86. bic r0, r0, #(0x1 << 11) /* disable Z, branch prediction */
  87. bic r0, r0, #(0x1 << 1) /* disable A, Strict alignment */
  88. /* check enabled. */
  89. mcr p15, 0, r0, c1, c0, 0 /* write CP15 register 1 */
  90. mov r0, r0
  91. mov r0, r0
  92. mov r0, r0
  93. mov r0, r0
  94. mmu_disable_notreq:
  95. NOP
  96. /* To return to ROM from plugin, we need to fill in these argument.
  97. * Here is what need to do:
  98. * Need to construct the paramters for this function before return to ROM:
  99. * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
  100. */
  101. pop {r0-r4, lr}
  102. push {r5}
  103. ldr r5, boot_data2
  104. str r5, [r0]
  105. ldr r5, image_len2
  106. str r5, [r1]
  107. ldr r5, second_ivt_offset
  108. str r5, [r2]
  109. mov r0, #1
  110. pop {r5}
  111. /* return back to ROM code */
  112. bx lr
  113. /* make the following data right in the end of the output*/
  114. .ltorg
  115. #if (defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT))
  116. #define FLASH_OFFSET 0x1000
  117. #else
  118. #define FLASH_OFFSET 0x400
  119. #endif
  120. /*
  121. * second_ivt_offset is the offset from the "second_ivt_header" to
  122. * "image_copy_start", which involves FLASH_OFFSET, plus the first
  123. * ivt_header, the plugin code size itself recorded by "ivt2_header"
  124. */
  125. second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET)
  126. /*
  127. * The following is the second IVT header plus the second boot data
  128. */
  129. ivt2_header: .long 0x0
  130. app2_code_jump_v: .long 0x0
  131. reserv3: .long 0x0
  132. dcd2_ptr: .long 0x0
  133. boot_data2_ptr: .long 0x0
  134. self_ptr2: .long 0x0
  135. app_code_csf2: .long 0x0
  136. reserv4: .long 0x0
  137. boot_data2: .long 0x0
  138. image_len2: .long 0x0
  139. plugin2: .long 0x0