cpu.c 2.6 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. /*
  9. * CPU test
  10. *
  11. * This test checks the arithmetic logic unit (ALU) of CPU.
  12. * It tests independently various groups of instructions using
  13. * run-time modification of the code to reduce the memory footprint.
  14. * For more details refer to post/cpu/ *.c files.
  15. */
  16. #include <watchdog.h>
  17. #include <post.h>
  18. #include <asm/mmu.h>
  19. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  20. extern int cpu_post_test_cmp (void);
  21. extern int cpu_post_test_cmpi (void);
  22. extern int cpu_post_test_two (void);
  23. extern int cpu_post_test_twox (void);
  24. extern int cpu_post_test_three (void);
  25. extern int cpu_post_test_threex (void);
  26. extern int cpu_post_test_threei (void);
  27. extern int cpu_post_test_andi (void);
  28. extern int cpu_post_test_srawi (void);
  29. extern int cpu_post_test_rlwnm (void);
  30. extern int cpu_post_test_rlwinm (void);
  31. extern int cpu_post_test_rlwimi (void);
  32. extern int cpu_post_test_store (void);
  33. extern int cpu_post_test_load (void);
  34. extern int cpu_post_test_cr (void);
  35. extern int cpu_post_test_b (void);
  36. extern int cpu_post_test_multi (void);
  37. extern int cpu_post_test_string (void);
  38. extern int cpu_post_test_complex (void);
  39. DECLARE_GLOBAL_DATA_PTR;
  40. ulong cpu_post_makecr (long v)
  41. {
  42. ulong cr = 0;
  43. if (v < 0)
  44. cr |= 0x80000000;
  45. if (v > 0)
  46. cr |= 0x40000000;
  47. if (v == 0)
  48. cr |= 0x20000000;
  49. return cr;
  50. }
  51. int cpu_post_test (int flags)
  52. {
  53. int ic = icache_status ();
  54. int ret = 0;
  55. WATCHDOG_RESET();
  56. if (ic)
  57. icache_disable ();
  58. if (ret == 0)
  59. ret = cpu_post_test_cmp ();
  60. if (ret == 0)
  61. ret = cpu_post_test_cmpi ();
  62. if (ret == 0)
  63. ret = cpu_post_test_two ();
  64. if (ret == 0)
  65. ret = cpu_post_test_twox ();
  66. WATCHDOG_RESET();
  67. if (ret == 0)
  68. ret = cpu_post_test_three ();
  69. if (ret == 0)
  70. ret = cpu_post_test_threex ();
  71. if (ret == 0)
  72. ret = cpu_post_test_threei ();
  73. if (ret == 0)
  74. ret = cpu_post_test_andi ();
  75. WATCHDOG_RESET();
  76. if (ret == 0)
  77. ret = cpu_post_test_srawi ();
  78. if (ret == 0)
  79. ret = cpu_post_test_rlwnm ();
  80. if (ret == 0)
  81. ret = cpu_post_test_rlwinm ();
  82. if (ret == 0)
  83. ret = cpu_post_test_rlwimi ();
  84. WATCHDOG_RESET();
  85. if (ret == 0)
  86. ret = cpu_post_test_store ();
  87. if (ret == 0)
  88. ret = cpu_post_test_load ();
  89. if (ret == 0)
  90. ret = cpu_post_test_cr ();
  91. if (ret == 0)
  92. ret = cpu_post_test_b ();
  93. WATCHDOG_RESET();
  94. if (ret == 0)
  95. ret = cpu_post_test_multi ();
  96. WATCHDOG_RESET();
  97. if (ret == 0)
  98. ret = cpu_post_test_string ();
  99. if (ret == 0)
  100. ret = cpu_post_test_complex ();
  101. WATCHDOG_RESET();
  102. if (ic)
  103. icache_enable ();
  104. WATCHDOG_RESET();
  105. return ret;
  106. }
  107. #endif /* CONFIG_POST & CONFIG_SYS_POST_CPU */