mmc.c 39 KB

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  1. /*
  2. * Copyright 2008, Freescale Semiconductor, Inc
  3. * Andy Fleming
  4. *
  5. * Based vaguely on the Linux code
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <command.h>
  12. #include <dm.h>
  13. #include <dm/device-internal.h>
  14. #include <errno.h>
  15. #include <mmc.h>
  16. #include <part.h>
  17. #include <malloc.h>
  18. #include <memalign.h>
  19. #include <linux/list.h>
  20. #include <div64.h>
  21. #include "mmc_private.h"
  22. static const unsigned int sd_au_size[] = {
  23. 0, SZ_16K / 512, SZ_32K / 512,
  24. SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
  25. SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
  26. SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
  27. SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
  28. };
  29. #ifndef CONFIG_DM_MMC_OPS
  30. __weak int board_mmc_getwp(struct mmc *mmc)
  31. {
  32. return -1;
  33. }
  34. int mmc_getwp(struct mmc *mmc)
  35. {
  36. int wp;
  37. wp = board_mmc_getwp(mmc);
  38. if (wp < 0) {
  39. if (mmc->cfg->ops->getwp)
  40. wp = mmc->cfg->ops->getwp(mmc);
  41. else
  42. wp = 0;
  43. }
  44. return wp;
  45. }
  46. __weak int board_mmc_getcd(struct mmc *mmc)
  47. {
  48. return -1;
  49. }
  50. #endif
  51. #ifdef CONFIG_MMC_TRACE
  52. void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
  53. {
  54. printf("CMD_SEND:%d\n", cmd->cmdidx);
  55. printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
  56. }
  57. void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
  58. {
  59. int i;
  60. u8 *ptr;
  61. if (ret) {
  62. printf("\t\tRET\t\t\t %d\n", ret);
  63. } else {
  64. switch (cmd->resp_type) {
  65. case MMC_RSP_NONE:
  66. printf("\t\tMMC_RSP_NONE\n");
  67. break;
  68. case MMC_RSP_R1:
  69. printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
  70. cmd->response[0]);
  71. break;
  72. case MMC_RSP_R1b:
  73. printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
  74. cmd->response[0]);
  75. break;
  76. case MMC_RSP_R2:
  77. printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
  78. cmd->response[0]);
  79. printf("\t\t \t\t 0x%08X \n",
  80. cmd->response[1]);
  81. printf("\t\t \t\t 0x%08X \n",
  82. cmd->response[2]);
  83. printf("\t\t \t\t 0x%08X \n",
  84. cmd->response[3]);
  85. printf("\n");
  86. printf("\t\t\t\t\tDUMPING DATA\n");
  87. for (i = 0; i < 4; i++) {
  88. int j;
  89. printf("\t\t\t\t\t%03d - ", i*4);
  90. ptr = (u8 *)&cmd->response[i];
  91. ptr += 3;
  92. for (j = 0; j < 4; j++)
  93. printf("%02X ", *ptr--);
  94. printf("\n");
  95. }
  96. break;
  97. case MMC_RSP_R3:
  98. printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
  99. cmd->response[0]);
  100. break;
  101. default:
  102. printf("\t\tERROR MMC rsp not supported\n");
  103. break;
  104. }
  105. }
  106. }
  107. void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
  108. {
  109. int status;
  110. status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
  111. printf("CURR STATE:%d\n", status);
  112. }
  113. #endif
  114. #ifndef CONFIG_DM_MMC_OPS
  115. int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  116. {
  117. int ret;
  118. mmmc_trace_before_send(mmc, cmd);
  119. ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
  120. mmmc_trace_after_send(mmc, cmd, ret);
  121. return ret;
  122. }
  123. #endif
  124. int mmc_send_status(struct mmc *mmc, int timeout)
  125. {
  126. struct mmc_cmd cmd;
  127. int err, retries = 5;
  128. cmd.cmdidx = MMC_CMD_SEND_STATUS;
  129. cmd.resp_type = MMC_RSP_R1;
  130. if (!mmc_host_is_spi(mmc))
  131. cmd.cmdarg = mmc->rca << 16;
  132. while (1) {
  133. err = mmc_send_cmd(mmc, &cmd, NULL);
  134. if (!err) {
  135. if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
  136. (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
  137. MMC_STATE_PRG)
  138. break;
  139. else if (cmd.response[0] & MMC_STATUS_MASK) {
  140. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  141. printf("Status Error: 0x%08X\n",
  142. cmd.response[0]);
  143. #endif
  144. return -ECOMM;
  145. }
  146. } else if (--retries < 0)
  147. return err;
  148. if (timeout-- <= 0)
  149. break;
  150. udelay(1000);
  151. }
  152. mmc_trace_state(mmc, &cmd);
  153. if (timeout <= 0) {
  154. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  155. printf("Timeout waiting card ready\n");
  156. #endif
  157. return -ETIMEDOUT;
  158. }
  159. return 0;
  160. }
  161. int mmc_set_blocklen(struct mmc *mmc, int len)
  162. {
  163. struct mmc_cmd cmd;
  164. if (mmc->ddr_mode)
  165. return 0;
  166. cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
  167. cmd.resp_type = MMC_RSP_R1;
  168. cmd.cmdarg = len;
  169. return mmc_send_cmd(mmc, &cmd, NULL);
  170. }
  171. static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
  172. lbaint_t blkcnt)
  173. {
  174. struct mmc_cmd cmd;
  175. struct mmc_data data;
  176. if (blkcnt > 1)
  177. cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
  178. else
  179. cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
  180. if (mmc->high_capacity)
  181. cmd.cmdarg = start;
  182. else
  183. cmd.cmdarg = start * mmc->read_bl_len;
  184. cmd.resp_type = MMC_RSP_R1;
  185. data.dest = dst;
  186. data.blocks = blkcnt;
  187. data.blocksize = mmc->read_bl_len;
  188. data.flags = MMC_DATA_READ;
  189. if (mmc_send_cmd(mmc, &cmd, &data))
  190. return 0;
  191. if (blkcnt > 1) {
  192. cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  193. cmd.cmdarg = 0;
  194. cmd.resp_type = MMC_RSP_R1b;
  195. if (mmc_send_cmd(mmc, &cmd, NULL)) {
  196. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  197. printf("mmc fail to send stop cmd\n");
  198. #endif
  199. return 0;
  200. }
  201. }
  202. return blkcnt;
  203. }
  204. #ifdef CONFIG_BLK
  205. ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
  206. #else
  207. ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
  208. void *dst)
  209. #endif
  210. {
  211. #ifdef CONFIG_BLK
  212. struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
  213. #endif
  214. int dev_num = block_dev->devnum;
  215. int err;
  216. lbaint_t cur, blocks_todo = blkcnt;
  217. if (blkcnt == 0)
  218. return 0;
  219. struct mmc *mmc = find_mmc_device(dev_num);
  220. if (!mmc)
  221. return 0;
  222. err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
  223. if (err < 0)
  224. return 0;
  225. if ((start + blkcnt) > block_dev->lba) {
  226. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  227. printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
  228. start + blkcnt, block_dev->lba);
  229. #endif
  230. return 0;
  231. }
  232. if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
  233. debug("%s: Failed to set blocklen\n", __func__);
  234. return 0;
  235. }
  236. do {
  237. cur = (blocks_todo > mmc->cfg->b_max) ?
  238. mmc->cfg->b_max : blocks_todo;
  239. if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
  240. debug("%s: Failed to read blocks\n", __func__);
  241. return 0;
  242. }
  243. blocks_todo -= cur;
  244. start += cur;
  245. dst += cur * mmc->read_bl_len;
  246. } while (blocks_todo > 0);
  247. return blkcnt;
  248. }
  249. static int mmc_go_idle(struct mmc *mmc)
  250. {
  251. struct mmc_cmd cmd;
  252. int err;
  253. udelay(1000);
  254. cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
  255. cmd.cmdarg = 0;
  256. cmd.resp_type = MMC_RSP_NONE;
  257. err = mmc_send_cmd(mmc, &cmd, NULL);
  258. if (err)
  259. return err;
  260. udelay(2000);
  261. return 0;
  262. }
  263. static int sd_send_op_cond(struct mmc *mmc)
  264. {
  265. int timeout = 1000;
  266. int err;
  267. struct mmc_cmd cmd;
  268. while (1) {
  269. cmd.cmdidx = MMC_CMD_APP_CMD;
  270. cmd.resp_type = MMC_RSP_R1;
  271. cmd.cmdarg = 0;
  272. err = mmc_send_cmd(mmc, &cmd, NULL);
  273. if (err)
  274. return err;
  275. cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
  276. cmd.resp_type = MMC_RSP_R3;
  277. /*
  278. * Most cards do not answer if some reserved bits
  279. * in the ocr are set. However, Some controller
  280. * can set bit 7 (reserved for low voltages), but
  281. * how to manage low voltages SD card is not yet
  282. * specified.
  283. */
  284. cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
  285. (mmc->cfg->voltages & 0xff8000);
  286. if (mmc->version == SD_VERSION_2)
  287. cmd.cmdarg |= OCR_HCS;
  288. err = mmc_send_cmd(mmc, &cmd, NULL);
  289. if (err)
  290. return err;
  291. if (cmd.response[0] & OCR_BUSY)
  292. break;
  293. if (timeout-- <= 0)
  294. return -EOPNOTSUPP;
  295. udelay(1000);
  296. }
  297. if (mmc->version != SD_VERSION_2)
  298. mmc->version = SD_VERSION_1_0;
  299. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  300. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  301. cmd.resp_type = MMC_RSP_R3;
  302. cmd.cmdarg = 0;
  303. err = mmc_send_cmd(mmc, &cmd, NULL);
  304. if (err)
  305. return err;
  306. }
  307. mmc->ocr = cmd.response[0];
  308. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  309. mmc->rca = 0;
  310. return 0;
  311. }
  312. static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
  313. {
  314. struct mmc_cmd cmd;
  315. int err;
  316. cmd.cmdidx = MMC_CMD_SEND_OP_COND;
  317. cmd.resp_type = MMC_RSP_R3;
  318. cmd.cmdarg = 0;
  319. if (use_arg && !mmc_host_is_spi(mmc))
  320. cmd.cmdarg = OCR_HCS |
  321. (mmc->cfg->voltages &
  322. (mmc->ocr & OCR_VOLTAGE_MASK)) |
  323. (mmc->ocr & OCR_ACCESS_MODE);
  324. err = mmc_send_cmd(mmc, &cmd, NULL);
  325. if (err)
  326. return err;
  327. mmc->ocr = cmd.response[0];
  328. return 0;
  329. }
  330. static int mmc_send_op_cond(struct mmc *mmc)
  331. {
  332. int err, i;
  333. /* Some cards seem to need this */
  334. mmc_go_idle(mmc);
  335. /* Asking to the card its capabilities */
  336. for (i = 0; i < 2; i++) {
  337. err = mmc_send_op_cond_iter(mmc, i != 0);
  338. if (err)
  339. return err;
  340. /* exit if not busy (flag seems to be inverted) */
  341. if (mmc->ocr & OCR_BUSY)
  342. break;
  343. }
  344. mmc->op_cond_pending = 1;
  345. return 0;
  346. }
  347. static int mmc_complete_op_cond(struct mmc *mmc)
  348. {
  349. struct mmc_cmd cmd;
  350. int timeout = 1000;
  351. uint start;
  352. int err;
  353. mmc->op_cond_pending = 0;
  354. if (!(mmc->ocr & OCR_BUSY)) {
  355. /* Some cards seem to need this */
  356. mmc_go_idle(mmc);
  357. start = get_timer(0);
  358. while (1) {
  359. err = mmc_send_op_cond_iter(mmc, 1);
  360. if (err)
  361. return err;
  362. if (mmc->ocr & OCR_BUSY)
  363. break;
  364. if (get_timer(start) > timeout)
  365. return -EOPNOTSUPP;
  366. udelay(100);
  367. }
  368. }
  369. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  370. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  371. cmd.resp_type = MMC_RSP_R3;
  372. cmd.cmdarg = 0;
  373. err = mmc_send_cmd(mmc, &cmd, NULL);
  374. if (err)
  375. return err;
  376. mmc->ocr = cmd.response[0];
  377. }
  378. mmc->version = MMC_VERSION_UNKNOWN;
  379. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  380. mmc->rca = 1;
  381. return 0;
  382. }
  383. static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
  384. {
  385. struct mmc_cmd cmd;
  386. struct mmc_data data;
  387. int err;
  388. /* Get the Card Status Register */
  389. cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
  390. cmd.resp_type = MMC_RSP_R1;
  391. cmd.cmdarg = 0;
  392. data.dest = (char *)ext_csd;
  393. data.blocks = 1;
  394. data.blocksize = MMC_MAX_BLOCK_LEN;
  395. data.flags = MMC_DATA_READ;
  396. err = mmc_send_cmd(mmc, &cmd, &data);
  397. return err;
  398. }
  399. int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
  400. {
  401. struct mmc_cmd cmd;
  402. int timeout = 1000;
  403. int ret;
  404. cmd.cmdidx = MMC_CMD_SWITCH;
  405. cmd.resp_type = MMC_RSP_R1b;
  406. cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
  407. (index << 16) |
  408. (value << 8);
  409. ret = mmc_send_cmd(mmc, &cmd, NULL);
  410. /* Waiting for the ready status */
  411. if (!ret)
  412. ret = mmc_send_status(mmc, timeout);
  413. return ret;
  414. }
  415. static int mmc_change_freq(struct mmc *mmc)
  416. {
  417. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  418. char cardtype;
  419. int err;
  420. mmc->card_caps = 0;
  421. if (mmc_host_is_spi(mmc))
  422. return 0;
  423. /* Only version 4 supports high-speed */
  424. if (mmc->version < MMC_VERSION_4)
  425. return 0;
  426. mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
  427. err = mmc_send_ext_csd(mmc, ext_csd);
  428. if (err)
  429. return err;
  430. cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
  431. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
  432. if (err)
  433. return err;
  434. /* Now check to see that it worked */
  435. err = mmc_send_ext_csd(mmc, ext_csd);
  436. if (err)
  437. return err;
  438. /* No high-speed support */
  439. if (!ext_csd[EXT_CSD_HS_TIMING])
  440. return 0;
  441. /* High Speed is set, there are two types: 52MHz and 26MHz */
  442. if (cardtype & EXT_CSD_CARD_TYPE_52) {
  443. if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
  444. mmc->card_caps |= MMC_MODE_DDR_52MHz;
  445. mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  446. } else {
  447. mmc->card_caps |= MMC_MODE_HS;
  448. }
  449. return 0;
  450. }
  451. static int mmc_set_capacity(struct mmc *mmc, int part_num)
  452. {
  453. switch (part_num) {
  454. case 0:
  455. mmc->capacity = mmc->capacity_user;
  456. break;
  457. case 1:
  458. case 2:
  459. mmc->capacity = mmc->capacity_boot;
  460. break;
  461. case 3:
  462. mmc->capacity = mmc->capacity_rpmb;
  463. break;
  464. case 4:
  465. case 5:
  466. case 6:
  467. case 7:
  468. mmc->capacity = mmc->capacity_gp[part_num - 4];
  469. break;
  470. default:
  471. return -1;
  472. }
  473. mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
  474. return 0;
  475. }
  476. int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
  477. {
  478. int ret;
  479. ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
  480. (mmc->part_config & ~PART_ACCESS_MASK)
  481. | (part_num & PART_ACCESS_MASK));
  482. /*
  483. * Set the capacity if the switch succeeded or was intended
  484. * to return to representing the raw device.
  485. */
  486. if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
  487. ret = mmc_set_capacity(mmc, part_num);
  488. mmc_get_blk_desc(mmc)->hwpart = part_num;
  489. }
  490. return ret;
  491. }
  492. int mmc_hwpart_config(struct mmc *mmc,
  493. const struct mmc_hwpart_conf *conf,
  494. enum mmc_hwpart_conf_mode mode)
  495. {
  496. u8 part_attrs = 0;
  497. u32 enh_size_mult;
  498. u32 enh_start_addr;
  499. u32 gp_size_mult[4];
  500. u32 max_enh_size_mult;
  501. u32 tot_enh_size_mult = 0;
  502. u8 wr_rel_set;
  503. int i, pidx, err;
  504. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  505. if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
  506. return -EINVAL;
  507. if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
  508. printf("eMMC >= 4.4 required for enhanced user data area\n");
  509. return -EMEDIUMTYPE;
  510. }
  511. if (!(mmc->part_support & PART_SUPPORT)) {
  512. printf("Card does not support partitioning\n");
  513. return -EMEDIUMTYPE;
  514. }
  515. if (!mmc->hc_wp_grp_size) {
  516. printf("Card does not define HC WP group size\n");
  517. return -EMEDIUMTYPE;
  518. }
  519. /* check partition alignment and total enhanced size */
  520. if (conf->user.enh_size) {
  521. if (conf->user.enh_size % mmc->hc_wp_grp_size ||
  522. conf->user.enh_start % mmc->hc_wp_grp_size) {
  523. printf("User data enhanced area not HC WP group "
  524. "size aligned\n");
  525. return -EINVAL;
  526. }
  527. part_attrs |= EXT_CSD_ENH_USR;
  528. enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
  529. if (mmc->high_capacity) {
  530. enh_start_addr = conf->user.enh_start;
  531. } else {
  532. enh_start_addr = (conf->user.enh_start << 9);
  533. }
  534. } else {
  535. enh_size_mult = 0;
  536. enh_start_addr = 0;
  537. }
  538. tot_enh_size_mult += enh_size_mult;
  539. for (pidx = 0; pidx < 4; pidx++) {
  540. if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
  541. printf("GP%i partition not HC WP group size "
  542. "aligned\n", pidx+1);
  543. return -EINVAL;
  544. }
  545. gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
  546. if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
  547. part_attrs |= EXT_CSD_ENH_GP(pidx);
  548. tot_enh_size_mult += gp_size_mult[pidx];
  549. }
  550. }
  551. if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
  552. printf("Card does not support enhanced attribute\n");
  553. return -EMEDIUMTYPE;
  554. }
  555. err = mmc_send_ext_csd(mmc, ext_csd);
  556. if (err)
  557. return err;
  558. max_enh_size_mult =
  559. (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
  560. (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
  561. ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
  562. if (tot_enh_size_mult > max_enh_size_mult) {
  563. printf("Total enhanced size exceeds maximum (%u > %u)\n",
  564. tot_enh_size_mult, max_enh_size_mult);
  565. return -EMEDIUMTYPE;
  566. }
  567. /* The default value of EXT_CSD_WR_REL_SET is device
  568. * dependent, the values can only be changed if the
  569. * EXT_CSD_HS_CTRL_REL bit is set. The values can be
  570. * changed only once and before partitioning is completed. */
  571. wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  572. if (conf->user.wr_rel_change) {
  573. if (conf->user.wr_rel_set)
  574. wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
  575. else
  576. wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
  577. }
  578. for (pidx = 0; pidx < 4; pidx++) {
  579. if (conf->gp_part[pidx].wr_rel_change) {
  580. if (conf->gp_part[pidx].wr_rel_set)
  581. wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
  582. else
  583. wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
  584. }
  585. }
  586. if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
  587. !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
  588. puts("Card does not support host controlled partition write "
  589. "reliability settings\n");
  590. return -EMEDIUMTYPE;
  591. }
  592. if (ext_csd[EXT_CSD_PARTITION_SETTING] &
  593. EXT_CSD_PARTITION_SETTING_COMPLETED) {
  594. printf("Card already partitioned\n");
  595. return -EPERM;
  596. }
  597. if (mode == MMC_HWPART_CONF_CHECK)
  598. return 0;
  599. /* Partitioning requires high-capacity size definitions */
  600. if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
  601. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  602. EXT_CSD_ERASE_GROUP_DEF, 1);
  603. if (err)
  604. return err;
  605. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  606. /* update erase group size to be high-capacity */
  607. mmc->erase_grp_size =
  608. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  609. }
  610. /* all OK, write the configuration */
  611. for (i = 0; i < 4; i++) {
  612. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  613. EXT_CSD_ENH_START_ADDR+i,
  614. (enh_start_addr >> (i*8)) & 0xFF);
  615. if (err)
  616. return err;
  617. }
  618. for (i = 0; i < 3; i++) {
  619. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  620. EXT_CSD_ENH_SIZE_MULT+i,
  621. (enh_size_mult >> (i*8)) & 0xFF);
  622. if (err)
  623. return err;
  624. }
  625. for (pidx = 0; pidx < 4; pidx++) {
  626. for (i = 0; i < 3; i++) {
  627. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  628. EXT_CSD_GP_SIZE_MULT+pidx*3+i,
  629. (gp_size_mult[pidx] >> (i*8)) & 0xFF);
  630. if (err)
  631. return err;
  632. }
  633. }
  634. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  635. EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
  636. if (err)
  637. return err;
  638. if (mode == MMC_HWPART_CONF_SET)
  639. return 0;
  640. /* The WR_REL_SET is a write-once register but shall be
  641. * written before setting PART_SETTING_COMPLETED. As it is
  642. * write-once we can only write it when completing the
  643. * partitioning. */
  644. if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
  645. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  646. EXT_CSD_WR_REL_SET, wr_rel_set);
  647. if (err)
  648. return err;
  649. }
  650. /* Setting PART_SETTING_COMPLETED confirms the partition
  651. * configuration but it only becomes effective after power
  652. * cycle, so we do not adjust the partition related settings
  653. * in the mmc struct. */
  654. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  655. EXT_CSD_PARTITION_SETTING,
  656. EXT_CSD_PARTITION_SETTING_COMPLETED);
  657. if (err)
  658. return err;
  659. return 0;
  660. }
  661. #ifndef CONFIG_DM_MMC_OPS
  662. int mmc_getcd(struct mmc *mmc)
  663. {
  664. int cd;
  665. cd = board_mmc_getcd(mmc);
  666. if (cd < 0) {
  667. if (mmc->cfg->ops->getcd)
  668. cd = mmc->cfg->ops->getcd(mmc);
  669. else
  670. cd = 1;
  671. }
  672. return cd;
  673. }
  674. #endif
  675. static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
  676. {
  677. struct mmc_cmd cmd;
  678. struct mmc_data data;
  679. /* Switch the frequency */
  680. cmd.cmdidx = SD_CMD_SWITCH_FUNC;
  681. cmd.resp_type = MMC_RSP_R1;
  682. cmd.cmdarg = (mode << 31) | 0xffffff;
  683. cmd.cmdarg &= ~(0xf << (group * 4));
  684. cmd.cmdarg |= value << (group * 4);
  685. data.dest = (char *)resp;
  686. data.blocksize = 64;
  687. data.blocks = 1;
  688. data.flags = MMC_DATA_READ;
  689. return mmc_send_cmd(mmc, &cmd, &data);
  690. }
  691. static int sd_change_freq(struct mmc *mmc)
  692. {
  693. int err;
  694. struct mmc_cmd cmd;
  695. ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
  696. ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
  697. struct mmc_data data;
  698. int timeout;
  699. mmc->card_caps = 0;
  700. if (mmc_host_is_spi(mmc))
  701. return 0;
  702. /* Read the SCR to find out if this card supports higher speeds */
  703. cmd.cmdidx = MMC_CMD_APP_CMD;
  704. cmd.resp_type = MMC_RSP_R1;
  705. cmd.cmdarg = mmc->rca << 16;
  706. err = mmc_send_cmd(mmc, &cmd, NULL);
  707. if (err)
  708. return err;
  709. cmd.cmdidx = SD_CMD_APP_SEND_SCR;
  710. cmd.resp_type = MMC_RSP_R1;
  711. cmd.cmdarg = 0;
  712. timeout = 3;
  713. retry_scr:
  714. data.dest = (char *)scr;
  715. data.blocksize = 8;
  716. data.blocks = 1;
  717. data.flags = MMC_DATA_READ;
  718. err = mmc_send_cmd(mmc, &cmd, &data);
  719. if (err) {
  720. if (timeout--)
  721. goto retry_scr;
  722. return err;
  723. }
  724. mmc->scr[0] = __be32_to_cpu(scr[0]);
  725. mmc->scr[1] = __be32_to_cpu(scr[1]);
  726. switch ((mmc->scr[0] >> 24) & 0xf) {
  727. case 0:
  728. mmc->version = SD_VERSION_1_0;
  729. break;
  730. case 1:
  731. mmc->version = SD_VERSION_1_10;
  732. break;
  733. case 2:
  734. mmc->version = SD_VERSION_2;
  735. if ((mmc->scr[0] >> 15) & 0x1)
  736. mmc->version = SD_VERSION_3;
  737. break;
  738. default:
  739. mmc->version = SD_VERSION_1_0;
  740. break;
  741. }
  742. if (mmc->scr[0] & SD_DATA_4BIT)
  743. mmc->card_caps |= MMC_MODE_4BIT;
  744. /* Version 1.0 doesn't support switching */
  745. if (mmc->version == SD_VERSION_1_0)
  746. return 0;
  747. timeout = 4;
  748. while (timeout--) {
  749. err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
  750. (u8 *)switch_status);
  751. if (err)
  752. return err;
  753. /* The high-speed function is busy. Try again */
  754. if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
  755. break;
  756. }
  757. /* If high-speed isn't supported, we return */
  758. if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
  759. return 0;
  760. /*
  761. * If the host doesn't support SD_HIGHSPEED, do not switch card to
  762. * HIGHSPEED mode even if the card support SD_HIGHSPPED.
  763. * This can avoid furthur problem when the card runs in different
  764. * mode between the host.
  765. */
  766. if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
  767. (mmc->cfg->host_caps & MMC_MODE_HS)))
  768. return 0;
  769. err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
  770. if (err)
  771. return err;
  772. if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
  773. mmc->card_caps |= MMC_MODE_HS;
  774. return 0;
  775. }
  776. static int sd_read_ssr(struct mmc *mmc)
  777. {
  778. int err, i;
  779. struct mmc_cmd cmd;
  780. ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
  781. struct mmc_data data;
  782. int timeout = 3;
  783. unsigned int au, eo, et, es;
  784. cmd.cmdidx = MMC_CMD_APP_CMD;
  785. cmd.resp_type = MMC_RSP_R1;
  786. cmd.cmdarg = mmc->rca << 16;
  787. err = mmc_send_cmd(mmc, &cmd, NULL);
  788. if (err)
  789. return err;
  790. cmd.cmdidx = SD_CMD_APP_SD_STATUS;
  791. cmd.resp_type = MMC_RSP_R1;
  792. cmd.cmdarg = 0;
  793. retry_ssr:
  794. data.dest = (char *)ssr;
  795. data.blocksize = 64;
  796. data.blocks = 1;
  797. data.flags = MMC_DATA_READ;
  798. err = mmc_send_cmd(mmc, &cmd, &data);
  799. if (err) {
  800. if (timeout--)
  801. goto retry_ssr;
  802. return err;
  803. }
  804. for (i = 0; i < 16; i++)
  805. ssr[i] = be32_to_cpu(ssr[i]);
  806. au = (ssr[2] >> 12) & 0xF;
  807. if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
  808. mmc->ssr.au = sd_au_size[au];
  809. es = (ssr[3] >> 24) & 0xFF;
  810. es |= (ssr[2] & 0xFF) << 8;
  811. et = (ssr[3] >> 18) & 0x3F;
  812. if (es && et) {
  813. eo = (ssr[3] >> 16) & 0x3;
  814. mmc->ssr.erase_timeout = (et * 1000) / es;
  815. mmc->ssr.erase_offset = eo * 1000;
  816. }
  817. } else {
  818. debug("Invalid Allocation Unit Size.\n");
  819. }
  820. return 0;
  821. }
  822. /* frequency bases */
  823. /* divided by 10 to be nice to platforms without floating point */
  824. static const int fbase[] = {
  825. 10000,
  826. 100000,
  827. 1000000,
  828. 10000000,
  829. };
  830. /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
  831. * to platforms without floating point.
  832. */
  833. static const u8 multipliers[] = {
  834. 0, /* reserved */
  835. 10,
  836. 12,
  837. 13,
  838. 15,
  839. 20,
  840. 25,
  841. 30,
  842. 35,
  843. 40,
  844. 45,
  845. 50,
  846. 55,
  847. 60,
  848. 70,
  849. 80,
  850. };
  851. #ifndef CONFIG_DM_MMC_OPS
  852. static void mmc_set_ios(struct mmc *mmc)
  853. {
  854. if (mmc->cfg->ops->set_ios)
  855. mmc->cfg->ops->set_ios(mmc);
  856. }
  857. #endif
  858. void mmc_set_clock(struct mmc *mmc, uint clock)
  859. {
  860. if (clock > mmc->cfg->f_max)
  861. clock = mmc->cfg->f_max;
  862. if (clock < mmc->cfg->f_min)
  863. clock = mmc->cfg->f_min;
  864. mmc->clock = clock;
  865. mmc_set_ios(mmc);
  866. }
  867. static void mmc_set_bus_width(struct mmc *mmc, uint width)
  868. {
  869. mmc->bus_width = width;
  870. mmc_set_ios(mmc);
  871. }
  872. static int mmc_startup(struct mmc *mmc)
  873. {
  874. int err, i;
  875. uint mult, freq;
  876. u64 cmult, csize, capacity;
  877. struct mmc_cmd cmd;
  878. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  879. ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
  880. int timeout = 1000;
  881. bool has_parts = false;
  882. bool part_completed;
  883. struct blk_desc *bdesc;
  884. #ifdef CONFIG_MMC_SPI_CRC_ON
  885. if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
  886. cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
  887. cmd.resp_type = MMC_RSP_R1;
  888. cmd.cmdarg = 1;
  889. err = mmc_send_cmd(mmc, &cmd, NULL);
  890. if (err)
  891. return err;
  892. }
  893. #endif
  894. /* Put the Card in Identify Mode */
  895. cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
  896. MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
  897. cmd.resp_type = MMC_RSP_R2;
  898. cmd.cmdarg = 0;
  899. err = mmc_send_cmd(mmc, &cmd, NULL);
  900. if (err)
  901. return err;
  902. memcpy(mmc->cid, cmd.response, 16);
  903. /*
  904. * For MMC cards, set the Relative Address.
  905. * For SD cards, get the Relatvie Address.
  906. * This also puts the cards into Standby State
  907. */
  908. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  909. cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
  910. cmd.cmdarg = mmc->rca << 16;
  911. cmd.resp_type = MMC_RSP_R6;
  912. err = mmc_send_cmd(mmc, &cmd, NULL);
  913. if (err)
  914. return err;
  915. if (IS_SD(mmc))
  916. mmc->rca = (cmd.response[0] >> 16) & 0xffff;
  917. }
  918. /* Get the Card-Specific Data */
  919. cmd.cmdidx = MMC_CMD_SEND_CSD;
  920. cmd.resp_type = MMC_RSP_R2;
  921. cmd.cmdarg = mmc->rca << 16;
  922. err = mmc_send_cmd(mmc, &cmd, NULL);
  923. /* Waiting for the ready status */
  924. mmc_send_status(mmc, timeout);
  925. if (err)
  926. return err;
  927. mmc->csd[0] = cmd.response[0];
  928. mmc->csd[1] = cmd.response[1];
  929. mmc->csd[2] = cmd.response[2];
  930. mmc->csd[3] = cmd.response[3];
  931. if (mmc->version == MMC_VERSION_UNKNOWN) {
  932. int version = (cmd.response[0] >> 26) & 0xf;
  933. switch (version) {
  934. case 0:
  935. mmc->version = MMC_VERSION_1_2;
  936. break;
  937. case 1:
  938. mmc->version = MMC_VERSION_1_4;
  939. break;
  940. case 2:
  941. mmc->version = MMC_VERSION_2_2;
  942. break;
  943. case 3:
  944. mmc->version = MMC_VERSION_3;
  945. break;
  946. case 4:
  947. mmc->version = MMC_VERSION_4;
  948. break;
  949. default:
  950. mmc->version = MMC_VERSION_1_2;
  951. break;
  952. }
  953. }
  954. /* divide frequency by 10, since the mults are 10x bigger */
  955. freq = fbase[(cmd.response[0] & 0x7)];
  956. mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
  957. mmc->tran_speed = freq * mult;
  958. mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
  959. mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
  960. if (IS_SD(mmc))
  961. mmc->write_bl_len = mmc->read_bl_len;
  962. else
  963. mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
  964. if (mmc->high_capacity) {
  965. csize = (mmc->csd[1] & 0x3f) << 16
  966. | (mmc->csd[2] & 0xffff0000) >> 16;
  967. cmult = 8;
  968. } else {
  969. csize = (mmc->csd[1] & 0x3ff) << 2
  970. | (mmc->csd[2] & 0xc0000000) >> 30;
  971. cmult = (mmc->csd[2] & 0x00038000) >> 15;
  972. }
  973. mmc->capacity_user = (csize + 1) << (cmult + 2);
  974. mmc->capacity_user *= mmc->read_bl_len;
  975. mmc->capacity_boot = 0;
  976. mmc->capacity_rpmb = 0;
  977. for (i = 0; i < 4; i++)
  978. mmc->capacity_gp[i] = 0;
  979. if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
  980. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  981. if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
  982. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  983. if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
  984. cmd.cmdidx = MMC_CMD_SET_DSR;
  985. cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
  986. cmd.resp_type = MMC_RSP_NONE;
  987. if (mmc_send_cmd(mmc, &cmd, NULL))
  988. printf("MMC: SET_DSR failed\n");
  989. }
  990. /* Select the card, and put it into Transfer Mode */
  991. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  992. cmd.cmdidx = MMC_CMD_SELECT_CARD;
  993. cmd.resp_type = MMC_RSP_R1;
  994. cmd.cmdarg = mmc->rca << 16;
  995. err = mmc_send_cmd(mmc, &cmd, NULL);
  996. if (err)
  997. return err;
  998. }
  999. /*
  1000. * For SD, its erase group is always one sector
  1001. */
  1002. mmc->erase_grp_size = 1;
  1003. mmc->part_config = MMCPART_NOAVAILABLE;
  1004. if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
  1005. /* check ext_csd version and capacity */
  1006. err = mmc_send_ext_csd(mmc, ext_csd);
  1007. if (err)
  1008. return err;
  1009. if (ext_csd[EXT_CSD_REV] >= 2) {
  1010. /*
  1011. * According to the JEDEC Standard, the value of
  1012. * ext_csd's capacity is valid if the value is more
  1013. * than 2GB
  1014. */
  1015. capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
  1016. | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
  1017. | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
  1018. | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
  1019. capacity *= MMC_MAX_BLOCK_LEN;
  1020. if ((capacity >> 20) > 2 * 1024)
  1021. mmc->capacity_user = capacity;
  1022. }
  1023. switch (ext_csd[EXT_CSD_REV]) {
  1024. case 1:
  1025. mmc->version = MMC_VERSION_4_1;
  1026. break;
  1027. case 2:
  1028. mmc->version = MMC_VERSION_4_2;
  1029. break;
  1030. case 3:
  1031. mmc->version = MMC_VERSION_4_3;
  1032. break;
  1033. case 5:
  1034. mmc->version = MMC_VERSION_4_41;
  1035. break;
  1036. case 6:
  1037. mmc->version = MMC_VERSION_4_5;
  1038. break;
  1039. case 7:
  1040. mmc->version = MMC_VERSION_5_0;
  1041. break;
  1042. case 8:
  1043. mmc->version = MMC_VERSION_5_1;
  1044. break;
  1045. }
  1046. /* The partition data may be non-zero but it is only
  1047. * effective if PARTITION_SETTING_COMPLETED is set in
  1048. * EXT_CSD, so ignore any data if this bit is not set,
  1049. * except for enabling the high-capacity group size
  1050. * definition (see below). */
  1051. part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
  1052. EXT_CSD_PARTITION_SETTING_COMPLETED);
  1053. /* store the partition info of emmc */
  1054. mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
  1055. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
  1056. ext_csd[EXT_CSD_BOOT_MULT])
  1057. mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
  1058. if (part_completed &&
  1059. (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
  1060. mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
  1061. mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
  1062. mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
  1063. for (i = 0; i < 4; i++) {
  1064. int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
  1065. uint mult = (ext_csd[idx + 2] << 16) +
  1066. (ext_csd[idx + 1] << 8) + ext_csd[idx];
  1067. if (mult)
  1068. has_parts = true;
  1069. if (!part_completed)
  1070. continue;
  1071. mmc->capacity_gp[i] = mult;
  1072. mmc->capacity_gp[i] *=
  1073. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  1074. mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1075. mmc->capacity_gp[i] <<= 19;
  1076. }
  1077. if (part_completed) {
  1078. mmc->enh_user_size =
  1079. (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
  1080. (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
  1081. ext_csd[EXT_CSD_ENH_SIZE_MULT];
  1082. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  1083. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1084. mmc->enh_user_size <<= 19;
  1085. mmc->enh_user_start =
  1086. (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
  1087. (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
  1088. (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
  1089. ext_csd[EXT_CSD_ENH_START_ADDR];
  1090. if (mmc->high_capacity)
  1091. mmc->enh_user_start <<= 9;
  1092. }
  1093. /*
  1094. * Host needs to enable ERASE_GRP_DEF bit if device is
  1095. * partitioned. This bit will be lost every time after a reset
  1096. * or power off. This will affect erase size.
  1097. */
  1098. if (part_completed)
  1099. has_parts = true;
  1100. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
  1101. (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
  1102. has_parts = true;
  1103. if (has_parts) {
  1104. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1105. EXT_CSD_ERASE_GROUP_DEF, 1);
  1106. if (err)
  1107. return err;
  1108. else
  1109. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  1110. }
  1111. if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
  1112. /* Read out group size from ext_csd */
  1113. mmc->erase_grp_size =
  1114. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  1115. /*
  1116. * if high capacity and partition setting completed
  1117. * SEC_COUNT is valid even if it is smaller than 2 GiB
  1118. * JEDEC Standard JESD84-B45, 6.2.4
  1119. */
  1120. if (mmc->high_capacity && part_completed) {
  1121. capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
  1122. (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
  1123. (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
  1124. (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
  1125. capacity *= MMC_MAX_BLOCK_LEN;
  1126. mmc->capacity_user = capacity;
  1127. }
  1128. } else {
  1129. /* Calculate the group size from the csd value. */
  1130. int erase_gsz, erase_gmul;
  1131. erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
  1132. erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
  1133. mmc->erase_grp_size = (erase_gsz + 1)
  1134. * (erase_gmul + 1);
  1135. }
  1136. mmc->hc_wp_grp_size = 1024
  1137. * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  1138. * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1139. mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  1140. }
  1141. err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
  1142. if (err)
  1143. return err;
  1144. if (IS_SD(mmc))
  1145. err = sd_change_freq(mmc);
  1146. else
  1147. err = mmc_change_freq(mmc);
  1148. if (err)
  1149. return err;
  1150. /* Restrict card's capabilities by what the host can do */
  1151. mmc->card_caps &= mmc->cfg->host_caps;
  1152. if (IS_SD(mmc)) {
  1153. if (mmc->card_caps & MMC_MODE_4BIT) {
  1154. cmd.cmdidx = MMC_CMD_APP_CMD;
  1155. cmd.resp_type = MMC_RSP_R1;
  1156. cmd.cmdarg = mmc->rca << 16;
  1157. err = mmc_send_cmd(mmc, &cmd, NULL);
  1158. if (err)
  1159. return err;
  1160. cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
  1161. cmd.resp_type = MMC_RSP_R1;
  1162. cmd.cmdarg = 2;
  1163. err = mmc_send_cmd(mmc, &cmd, NULL);
  1164. if (err)
  1165. return err;
  1166. mmc_set_bus_width(mmc, 4);
  1167. }
  1168. err = sd_read_ssr(mmc);
  1169. if (err)
  1170. return err;
  1171. if (mmc->card_caps & MMC_MODE_HS)
  1172. mmc->tran_speed = 50000000;
  1173. else
  1174. mmc->tran_speed = 25000000;
  1175. } else if (mmc->version >= MMC_VERSION_4) {
  1176. /* Only version 4 of MMC supports wider bus widths */
  1177. int idx;
  1178. /* An array of possible bus widths in order of preference */
  1179. static unsigned ext_csd_bits[] = {
  1180. EXT_CSD_DDR_BUS_WIDTH_8,
  1181. EXT_CSD_DDR_BUS_WIDTH_4,
  1182. EXT_CSD_BUS_WIDTH_8,
  1183. EXT_CSD_BUS_WIDTH_4,
  1184. EXT_CSD_BUS_WIDTH_1,
  1185. };
  1186. /* An array to map CSD bus widths to host cap bits */
  1187. static unsigned ext_to_hostcaps[] = {
  1188. [EXT_CSD_DDR_BUS_WIDTH_4] =
  1189. MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
  1190. [EXT_CSD_DDR_BUS_WIDTH_8] =
  1191. MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
  1192. [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
  1193. [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
  1194. };
  1195. /* An array to map chosen bus width to an integer */
  1196. static unsigned widths[] = {
  1197. 8, 4, 8, 4, 1,
  1198. };
  1199. for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
  1200. unsigned int extw = ext_csd_bits[idx];
  1201. unsigned int caps = ext_to_hostcaps[extw];
  1202. /*
  1203. * If the bus width is still not changed,
  1204. * don't try to set the default again.
  1205. * Otherwise, recover from switch attempts
  1206. * by switching to 1-bit bus width.
  1207. */
  1208. if (extw == EXT_CSD_BUS_WIDTH_1 &&
  1209. mmc->bus_width == 1) {
  1210. err = 0;
  1211. break;
  1212. }
  1213. /*
  1214. * Check to make sure the card and controller support
  1215. * these capabilities
  1216. */
  1217. if ((mmc->card_caps & caps) != caps)
  1218. continue;
  1219. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1220. EXT_CSD_BUS_WIDTH, extw);
  1221. if (err)
  1222. continue;
  1223. mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
  1224. mmc_set_bus_width(mmc, widths[idx]);
  1225. err = mmc_send_ext_csd(mmc, test_csd);
  1226. if (err)
  1227. continue;
  1228. /* Only compare read only fields */
  1229. if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
  1230. == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
  1231. ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
  1232. == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
  1233. ext_csd[EXT_CSD_REV]
  1234. == test_csd[EXT_CSD_REV] &&
  1235. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  1236. == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
  1237. memcmp(&ext_csd[EXT_CSD_SEC_CNT],
  1238. &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
  1239. break;
  1240. else
  1241. err = -EBADMSG;
  1242. }
  1243. if (err)
  1244. return err;
  1245. if (mmc->card_caps & MMC_MODE_HS) {
  1246. if (mmc->card_caps & MMC_MODE_HS_52MHz)
  1247. mmc->tran_speed = 52000000;
  1248. else
  1249. mmc->tran_speed = 26000000;
  1250. }
  1251. }
  1252. mmc_set_clock(mmc, mmc->tran_speed);
  1253. /* Fix the block length for DDR mode */
  1254. if (mmc->ddr_mode) {
  1255. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  1256. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  1257. }
  1258. /* fill in device description */
  1259. bdesc = mmc_get_blk_desc(mmc);
  1260. bdesc->lun = 0;
  1261. bdesc->hwpart = 0;
  1262. bdesc->type = 0;
  1263. bdesc->blksz = mmc->read_bl_len;
  1264. bdesc->log2blksz = LOG2(bdesc->blksz);
  1265. bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
  1266. #if !defined(CONFIG_SPL_BUILD) || \
  1267. (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
  1268. !defined(CONFIG_USE_TINY_PRINTF))
  1269. sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
  1270. mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
  1271. (mmc->cid[3] >> 16) & 0xffff);
  1272. sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
  1273. (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
  1274. (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
  1275. (mmc->cid[2] >> 24) & 0xff);
  1276. sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
  1277. (mmc->cid[2] >> 16) & 0xf);
  1278. #else
  1279. bdesc->vendor[0] = 0;
  1280. bdesc->product[0] = 0;
  1281. bdesc->revision[0] = 0;
  1282. #endif
  1283. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
  1284. part_init(bdesc);
  1285. #endif
  1286. return 0;
  1287. }
  1288. static int mmc_send_if_cond(struct mmc *mmc)
  1289. {
  1290. struct mmc_cmd cmd;
  1291. int err;
  1292. cmd.cmdidx = SD_CMD_SEND_IF_COND;
  1293. /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
  1294. cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
  1295. cmd.resp_type = MMC_RSP_R7;
  1296. err = mmc_send_cmd(mmc, &cmd, NULL);
  1297. if (err)
  1298. return err;
  1299. if ((cmd.response[0] & 0xff) != 0xaa)
  1300. return -EOPNOTSUPP;
  1301. else
  1302. mmc->version = SD_VERSION_2;
  1303. return 0;
  1304. }
  1305. /* board-specific MMC power initializations. */
  1306. __weak void board_mmc_power_init(void)
  1307. {
  1308. }
  1309. int mmc_start_init(struct mmc *mmc)
  1310. {
  1311. bool no_card;
  1312. int err;
  1313. /* we pretend there's no card when init is NULL */
  1314. no_card = mmc_getcd(mmc) == 0;
  1315. #ifndef CONFIG_DM_MMC_OPS
  1316. no_card = no_card || (mmc->cfg->ops->init == NULL);
  1317. #endif
  1318. if (no_card) {
  1319. mmc->has_init = 0;
  1320. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  1321. printf("MMC: no card present\n");
  1322. #endif
  1323. return -ENOMEDIUM;
  1324. }
  1325. if (mmc->has_init)
  1326. return 0;
  1327. #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  1328. mmc_adapter_card_type_ident();
  1329. #endif
  1330. board_mmc_power_init();
  1331. #ifdef CONFIG_DM_MMC_OPS
  1332. /* The device has already been probed ready for use */
  1333. #else
  1334. /* made sure it's not NULL earlier */
  1335. err = mmc->cfg->ops->init(mmc);
  1336. if (err)
  1337. return err;
  1338. #endif
  1339. mmc->ddr_mode = 0;
  1340. mmc_set_bus_width(mmc, 1);
  1341. mmc_set_clock(mmc, 1);
  1342. /* Reset the Card */
  1343. err = mmc_go_idle(mmc);
  1344. if (err)
  1345. return err;
  1346. /* The internal partition reset to user partition(0) at every CMD0*/
  1347. mmc_get_blk_desc(mmc)->hwpart = 0;
  1348. /* Test for SD version 2 */
  1349. err = mmc_send_if_cond(mmc);
  1350. /* Now try to get the SD card's operating condition */
  1351. err = sd_send_op_cond(mmc);
  1352. /* If the command timed out, we check for an MMC card */
  1353. if (err == -ETIMEDOUT) {
  1354. err = mmc_send_op_cond(mmc);
  1355. if (err) {
  1356. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  1357. printf("Card did not respond to voltage select!\n");
  1358. #endif
  1359. return -EOPNOTSUPP;
  1360. }
  1361. }
  1362. if (!err)
  1363. mmc->init_in_progress = 1;
  1364. return err;
  1365. }
  1366. static int mmc_complete_init(struct mmc *mmc)
  1367. {
  1368. int err = 0;
  1369. mmc->init_in_progress = 0;
  1370. if (mmc->op_cond_pending)
  1371. err = mmc_complete_op_cond(mmc);
  1372. if (!err)
  1373. err = mmc_startup(mmc);
  1374. if (err)
  1375. mmc->has_init = 0;
  1376. else
  1377. mmc->has_init = 1;
  1378. return err;
  1379. }
  1380. int mmc_init(struct mmc *mmc)
  1381. {
  1382. int err = 0;
  1383. unsigned start;
  1384. #ifdef CONFIG_DM_MMC
  1385. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
  1386. upriv->mmc = mmc;
  1387. #endif
  1388. if (mmc->has_init)
  1389. return 0;
  1390. start = get_timer(0);
  1391. if (!mmc->init_in_progress)
  1392. err = mmc_start_init(mmc);
  1393. if (!err)
  1394. err = mmc_complete_init(mmc);
  1395. debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
  1396. return err;
  1397. }
  1398. int mmc_set_dsr(struct mmc *mmc, u16 val)
  1399. {
  1400. mmc->dsr = val;
  1401. return 0;
  1402. }
  1403. /* CPU-specific MMC initializations */
  1404. __weak int cpu_mmc_init(bd_t *bis)
  1405. {
  1406. return -1;
  1407. }
  1408. /* board-specific MMC initializations. */
  1409. __weak int board_mmc_init(bd_t *bis)
  1410. {
  1411. return -1;
  1412. }
  1413. void mmc_set_preinit(struct mmc *mmc, int preinit)
  1414. {
  1415. mmc->preinit = preinit;
  1416. }
  1417. #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
  1418. static int mmc_probe(bd_t *bis)
  1419. {
  1420. return 0;
  1421. }
  1422. #elif defined(CONFIG_DM_MMC)
  1423. static int mmc_probe(bd_t *bis)
  1424. {
  1425. int ret, i;
  1426. struct uclass *uc;
  1427. struct udevice *dev;
  1428. ret = uclass_get(UCLASS_MMC, &uc);
  1429. if (ret)
  1430. return ret;
  1431. /*
  1432. * Try to add them in sequence order. Really with driver model we
  1433. * should allow holes, but the current MMC list does not allow that.
  1434. * So if we request 0, 1, 3 we will get 0, 1, 2.
  1435. */
  1436. for (i = 0; ; i++) {
  1437. ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
  1438. if (ret == -ENODEV)
  1439. break;
  1440. }
  1441. uclass_foreach_dev(dev, uc) {
  1442. ret = device_probe(dev);
  1443. if (ret)
  1444. printf("%s - probe failed: %d\n", dev->name, ret);
  1445. }
  1446. return 0;
  1447. }
  1448. #else
  1449. static int mmc_probe(bd_t *bis)
  1450. {
  1451. if (board_mmc_init(bis) < 0)
  1452. cpu_mmc_init(bis);
  1453. return 0;
  1454. }
  1455. #endif
  1456. int mmc_initialize(bd_t *bis)
  1457. {
  1458. static int initialized = 0;
  1459. int ret;
  1460. if (initialized) /* Avoid initializing mmc multiple times */
  1461. return 0;
  1462. initialized = 1;
  1463. #ifndef CONFIG_BLK
  1464. mmc_list_init();
  1465. #endif
  1466. ret = mmc_probe(bis);
  1467. if (ret)
  1468. return ret;
  1469. #ifndef CONFIG_SPL_BUILD
  1470. print_mmc_devices(',');
  1471. #endif
  1472. mmc_do_preinit();
  1473. return 0;
  1474. }