i2c-uniphier.c 4.9 KB

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  1. /*
  2. * Copyright (C) 2014 Panasonic Corporation
  3. * Copyright (C) 2015-2016 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <linux/types.h>
  11. #include <linux/io.h>
  12. #include <linux/sizes.h>
  13. #include <linux/errno.h>
  14. #include <i2c.h>
  15. #include <fdtdec.h>
  16. struct uniphier_i2c_regs {
  17. u32 dtrm; /* data transmission */
  18. #define I2C_DTRM_STA (1 << 10)
  19. #define I2C_DTRM_STO (1 << 9)
  20. #define I2C_DTRM_NACK (1 << 8)
  21. #define I2C_DTRM_RD (1 << 0)
  22. u32 drec; /* data reception */
  23. #define I2C_DREC_STS (1 << 12)
  24. #define I2C_DREC_LRB (1 << 11)
  25. #define I2C_DREC_LAB (1 << 9)
  26. u32 myad; /* slave address */
  27. u32 clk; /* clock frequency control */
  28. u32 brst; /* bus reset */
  29. #define I2C_BRST_FOEN (1 << 1)
  30. #define I2C_BRST_BRST (1 << 0)
  31. u32 hold; /* hold time control */
  32. u32 bsts; /* bus status monitor */
  33. u32 noise; /* noise filter control */
  34. u32 setup; /* setup time control */
  35. };
  36. #define IOBUS_FREQ 100000000
  37. struct uniphier_i2c_dev {
  38. struct uniphier_i2c_regs __iomem *regs; /* register base */
  39. unsigned long input_clk; /* master clock (Hz) */
  40. unsigned long wait_us; /* wait for every byte transfer (us) */
  41. };
  42. static int uniphier_i2c_probe(struct udevice *dev)
  43. {
  44. fdt_addr_t addr;
  45. struct uniphier_i2c_dev *priv = dev_get_priv(dev);
  46. addr = devfdt_get_addr(dev);
  47. if (addr == FDT_ADDR_T_NONE)
  48. return -EINVAL;
  49. priv->regs = devm_ioremap(dev, addr, SZ_64);
  50. if (!priv->regs)
  51. return -ENOMEM;
  52. priv->input_clk = IOBUS_FREQ;
  53. /* deassert reset */
  54. writel(0x3, &priv->regs->brst);
  55. return 0;
  56. }
  57. static int send_and_recv_byte(struct uniphier_i2c_dev *dev, u32 dtrm)
  58. {
  59. writel(dtrm, &dev->regs->dtrm);
  60. /*
  61. * This controller only provides interruption to inform the completion
  62. * of each byte transfer. (No status register to poll it.)
  63. * Unfortunately, U-Boot does not have a good support of interrupt.
  64. * Wait for a while.
  65. */
  66. udelay(dev->wait_us);
  67. return readl(&dev->regs->drec);
  68. }
  69. static int send_byte(struct uniphier_i2c_dev *dev, u32 dtrm, bool *stop)
  70. {
  71. int ret = 0;
  72. u32 drec;
  73. drec = send_and_recv_byte(dev, dtrm);
  74. if (drec & I2C_DREC_LAB) {
  75. debug("uniphier_i2c: bus arbitration failed\n");
  76. *stop = false;
  77. ret = -EREMOTEIO;
  78. }
  79. if (drec & I2C_DREC_LRB) {
  80. debug("uniphier_i2c: slave did not return ACK\n");
  81. ret = -EREMOTEIO;
  82. }
  83. return ret;
  84. }
  85. static int uniphier_i2c_transmit(struct uniphier_i2c_dev *dev, uint addr,
  86. uint len, const u8 *buf, bool *stop)
  87. {
  88. int ret;
  89. debug("%s: addr = %x, len = %d\n", __func__, addr, len);
  90. ret = send_byte(dev, I2C_DTRM_STA | I2C_DTRM_NACK | addr << 1, stop);
  91. if (ret < 0)
  92. goto fail;
  93. while (len--) {
  94. ret = send_byte(dev, I2C_DTRM_NACK | *buf++, stop);
  95. if (ret < 0)
  96. goto fail;
  97. }
  98. fail:
  99. if (*stop)
  100. writel(I2C_DTRM_STO | I2C_DTRM_NACK, &dev->regs->dtrm);
  101. return ret;
  102. }
  103. static int uniphier_i2c_receive(struct uniphier_i2c_dev *dev, uint addr,
  104. uint len, u8 *buf, bool *stop)
  105. {
  106. int ret;
  107. debug("%s: addr = %x, len = %d\n", __func__, addr, len);
  108. ret = send_byte(dev, I2C_DTRM_STA | I2C_DTRM_NACK |
  109. I2C_DTRM_RD | addr << 1, stop);
  110. if (ret < 0)
  111. goto fail;
  112. while (len--)
  113. *buf++ = send_and_recv_byte(dev, len ? 0 : I2C_DTRM_NACK);
  114. fail:
  115. if (*stop)
  116. writel(I2C_DTRM_STO | I2C_DTRM_NACK, &dev->regs->dtrm);
  117. return ret;
  118. }
  119. static int uniphier_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  120. int nmsgs)
  121. {
  122. int ret = 0;
  123. struct uniphier_i2c_dev *dev = dev_get_priv(bus);
  124. bool stop;
  125. for (; nmsgs > 0; nmsgs--, msg++) {
  126. /* If next message is read, skip the stop condition */
  127. stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
  128. if (msg->flags & I2C_M_RD)
  129. ret = uniphier_i2c_receive(dev, msg->addr, msg->len,
  130. msg->buf, &stop);
  131. else
  132. ret = uniphier_i2c_transmit(dev, msg->addr, msg->len,
  133. msg->buf, &stop);
  134. if (ret < 0)
  135. break;
  136. }
  137. return ret;
  138. }
  139. static int uniphier_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  140. {
  141. struct uniphier_i2c_dev *priv = dev_get_priv(bus);
  142. /* max supported frequency is 400 kHz */
  143. if (speed > 400000)
  144. return -EINVAL;
  145. /* bus reset: make sure the bus is idle when change the frequency */
  146. writel(0x1, &priv->regs->brst);
  147. writel((priv->input_clk / speed / 2 << 16) | (priv->input_clk / speed),
  148. &priv->regs->clk);
  149. writel(0x3, &priv->regs->brst);
  150. /*
  151. * Theoretically, each byte can be transferred in
  152. * 1000000 * 9 / speed usec. For safety, wait more than double.
  153. */
  154. priv->wait_us = 20000000 / speed;
  155. return 0;
  156. }
  157. static const struct dm_i2c_ops uniphier_i2c_ops = {
  158. .xfer = uniphier_i2c_xfer,
  159. .set_bus_speed = uniphier_i2c_set_bus_speed,
  160. };
  161. static const struct udevice_id uniphier_i2c_of_match[] = {
  162. { .compatible = "socionext,uniphier-i2c" },
  163. { /* sentinel */ }
  164. };
  165. U_BOOT_DRIVER(uniphier_i2c) = {
  166. .name = "uniphier-i2c",
  167. .id = UCLASS_I2C,
  168. .of_match = uniphier_i2c_of_match,
  169. .probe = uniphier_i2c_probe,
  170. .priv_auto_alloc_size = sizeof(struct uniphier_i2c_dev),
  171. .ops = &uniphier_i2c_ops,
  172. };