sunxi_nand_spl.c 10 KB

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  1. /*
  2. * Copyright (c) 2014-2015, Antmicro Ltd <www.antmicro.com>
  3. * Copyright (c) 2015, AW-SOM Technologies <www.aw-som.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <config.h>
  9. #include <asm/io.h>
  10. #include <nand.h>
  11. /* registers */
  12. #define NFC_CTL 0x00000000
  13. #define NFC_ST 0x00000004
  14. #define NFC_INT 0x00000008
  15. #define NFC_TIMING_CTL 0x0000000C
  16. #define NFC_TIMING_CFG 0x00000010
  17. #define NFC_ADDR_LOW 0x00000014
  18. #define NFC_ADDR_HIGH 0x00000018
  19. #define NFC_SECTOR_NUM 0x0000001C
  20. #define NFC_CNT 0x00000020
  21. #define NFC_CMD 0x00000024
  22. #define NFC_RCMD_SET 0x00000028
  23. #define NFC_WCMD_SET 0x0000002C
  24. #define NFC_IO_DATA 0x00000030
  25. #define NFC_ECC_CTL 0x00000034
  26. #define NFC_ECC_ST 0x00000038
  27. #define NFC_DEBUG 0x0000003C
  28. #define NFC_ECC_CNT0 0x00000040
  29. #define NFC_ECC_CNT1 0x00000044
  30. #define NFC_ECC_CNT2 0x00000048
  31. #define NFC_ECC_CNT3 0x0000004C
  32. #define NFC_USER_DATA_BASE 0x00000050
  33. #define NFC_EFNAND_STATUS 0x00000090
  34. #define NFC_SPARE_AREA 0x000000A0
  35. #define NFC_PATTERN_ID 0x000000A4
  36. #define NFC_RAM0_BASE 0x00000400
  37. #define NFC_RAM1_BASE 0x00000800
  38. #define NFC_CTL_EN (1 << 0)
  39. #define NFC_CTL_RESET (1 << 1)
  40. #define NFC_CTL_RAM_METHOD (1 << 14)
  41. #define NFC_ECC_EN (1 << 0)
  42. #define NFC_ECC_PIPELINE (1 << 3)
  43. #define NFC_ECC_EXCEPTION (1 << 4)
  44. #define NFC_ECC_BLOCK_SIZE (1 << 5)
  45. #define NFC_ECC_RANDOM_EN (1 << 9)
  46. #define NFC_ECC_RANDOM_DIRECTION (1 << 10)
  47. #define NFC_ADDR_NUM_OFFSET 16
  48. #define NFC_SEND_ADR (1 << 19)
  49. #define NFC_ACCESS_DIR (1 << 20)
  50. #define NFC_DATA_TRANS (1 << 21)
  51. #define NFC_SEND_CMD1 (1 << 22)
  52. #define NFC_WAIT_FLAG (1 << 23)
  53. #define NFC_SEND_CMD2 (1 << 24)
  54. #define NFC_SEQ (1 << 25)
  55. #define NFC_DATA_SWAP_METHOD (1 << 26)
  56. #define NFC_ROW_AUTO_INC (1 << 27)
  57. #define NFC_SEND_CMD3 (1 << 28)
  58. #define NFC_SEND_CMD4 (1 << 29)
  59. #define NFC_CMD_INT_FLAG (1 << 1)
  60. #define NFC_READ_CMD_OFFSET 0
  61. #define NFC_RANDOM_READ_CMD0_OFFSET 8
  62. #define NFC_RANDOM_READ_CMD1_OFFSET 16
  63. #define NFC_CMD_RNDOUTSTART 0xE0
  64. #define NFC_CMD_RNDOUT 0x05
  65. #define NFC_CMD_READSTART 0x30
  66. #define NFC_PAGE_CMD (2 << 30)
  67. #define SUNXI_DMA_CFG_REG0 0x300
  68. #define SUNXI_DMA_SRC_START_ADDR_REG0 0x304
  69. #define SUNXI_DMA_DEST_START_ADDRR_REG0 0x308
  70. #define SUNXI_DMA_DDMA_BC_REG0 0x30C
  71. #define SUNXI_DMA_DDMA_PARA_REG0 0x318
  72. #define SUNXI_DMA_DDMA_CFG_REG_LOADING (1 << 31)
  73. #define SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 (2 << 25)
  74. #define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 (2 << 9)
  75. #define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO (1 << 5)
  76. #define SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC (3 << 0)
  77. #define SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC (0x0F << 0)
  78. #define SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE (0x7F << 8)
  79. /* minimal "boot0" style NAND support for Allwinner A20 */
  80. /* temporary buffer in internal ram */
  81. unsigned char temp_buf[CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE]
  82. __aligned(0x10) __section(".text#");
  83. /* random seed used by linux */
  84. const uint16_t random_seed[128] = {
  85. 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
  86. 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
  87. 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
  88. 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
  89. 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
  90. 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
  91. 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
  92. 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
  93. 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
  94. 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
  95. 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
  96. 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
  97. 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
  98. 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
  99. 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
  100. 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
  101. };
  102. /* random seed used for syndrome calls */
  103. const uint16_t random_seed_syndrome = 0x4a80;
  104. #define MAX_RETRIES 10
  105. static int check_value_inner(int offset, int expected_bits,
  106. int max_number_of_retries, int negation)
  107. {
  108. int retries = 0;
  109. do {
  110. int val = readl(offset) & expected_bits;
  111. if (negation ? !val : val)
  112. return 1;
  113. mdelay(1);
  114. retries++;
  115. } while (retries < max_number_of_retries);
  116. return 0;
  117. }
  118. static inline int check_value(int offset, int expected_bits,
  119. int max_number_of_retries)
  120. {
  121. return check_value_inner(offset, expected_bits,
  122. max_number_of_retries, 0);
  123. }
  124. static inline int check_value_negated(int offset, int unexpected_bits,
  125. int max_number_of_retries)
  126. {
  127. return check_value_inner(offset, unexpected_bits,
  128. max_number_of_retries, 1);
  129. }
  130. void nand_init(void)
  131. {
  132. uint32_t val;
  133. val = readl(SUNXI_NFC_BASE + NFC_CTL);
  134. /* enable and reset CTL */
  135. writel(val | NFC_CTL_EN | NFC_CTL_RESET,
  136. SUNXI_NFC_BASE + NFC_CTL);
  137. if (!check_value_negated(SUNXI_NFC_BASE + NFC_CTL,
  138. NFC_CTL_RESET, MAX_RETRIES)) {
  139. printf("Couldn't initialize nand\n");
  140. }
  141. }
  142. static void nand_read_page(unsigned int real_addr, int syndrome,
  143. uint32_t *ecc_errors)
  144. {
  145. uint32_t val;
  146. int ecc_off = 0;
  147. uint16_t ecc_mode = 0;
  148. uint16_t rand_seed;
  149. uint32_t page;
  150. uint16_t column;
  151. uint32_t oob_offset;
  152. switch (CONFIG_NAND_SUNXI_SPL_ECC_STRENGTH) {
  153. case 16:
  154. ecc_mode = 0;
  155. ecc_off = 0x20;
  156. break;
  157. case 24:
  158. ecc_mode = 1;
  159. ecc_off = 0x2e;
  160. break;
  161. case 28:
  162. ecc_mode = 2;
  163. ecc_off = 0x32;
  164. break;
  165. case 32:
  166. ecc_mode = 3;
  167. ecc_off = 0x3c;
  168. break;
  169. case 40:
  170. ecc_mode = 4;
  171. ecc_off = 0x4a;
  172. break;
  173. case 48:
  174. ecc_mode = 4;
  175. ecc_off = 0x52;
  176. break;
  177. case 56:
  178. ecc_mode = 4;
  179. ecc_off = 0x60;
  180. break;
  181. case 60:
  182. ecc_mode = 4;
  183. ecc_off = 0x0;
  184. break;
  185. case 64:
  186. ecc_mode = 4;
  187. ecc_off = 0x0;
  188. break;
  189. default:
  190. ecc_mode = 0;
  191. ecc_off = 0;
  192. }
  193. if (ecc_off == 0) {
  194. printf("Unsupported ECC strength (%d)!\n",
  195. CONFIG_NAND_SUNXI_SPL_ECC_STRENGTH);
  196. return;
  197. }
  198. /* clear temp_buf */
  199. memset(temp_buf, 0, CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE);
  200. /* set CMD */
  201. writel(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET,
  202. SUNXI_NFC_BASE + NFC_CMD);
  203. if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_CMD_INT_FLAG,
  204. MAX_RETRIES)) {
  205. printf("Error while initilizing command interrupt\n");
  206. return;
  207. }
  208. page = real_addr / CONFIG_NAND_SUNXI_SPL_PAGE_SIZE;
  209. column = real_addr % CONFIG_NAND_SUNXI_SPL_PAGE_SIZE;
  210. if (syndrome)
  211. column += (column / CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
  212. * ecc_off;
  213. /* clear ecc status */
  214. writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
  215. /* Choose correct seed */
  216. if (syndrome)
  217. rand_seed = random_seed_syndrome;
  218. else
  219. rand_seed = random_seed[page % 128];
  220. writel((rand_seed << 16) | NFC_ECC_RANDOM_EN | NFC_ECC_EN
  221. | NFC_ECC_PIPELINE | (ecc_mode << 12),
  222. SUNXI_NFC_BASE + NFC_ECC_CTL);
  223. val = readl(SUNXI_NFC_BASE + NFC_CTL);
  224. writel(val | NFC_CTL_RAM_METHOD, SUNXI_NFC_BASE + NFC_CTL);
  225. if (syndrome) {
  226. writel(CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE,
  227. SUNXI_NFC_BASE + NFC_SPARE_AREA);
  228. } else {
  229. oob_offset = CONFIG_NAND_SUNXI_SPL_PAGE_SIZE
  230. + (column / CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
  231. * ecc_off;
  232. writel(oob_offset, SUNXI_NFC_BASE + NFC_SPARE_AREA);
  233. }
  234. /* SUNXI_DMA */
  235. writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */
  236. /* read from REG_IO_DATA */
  237. writel(SUNXI_NFC_BASE + NFC_IO_DATA,
  238. SUNXI_DMA_BASE + SUNXI_DMA_SRC_START_ADDR_REG0);
  239. /* read to RAM */
  240. writel((uint32_t)temp_buf,
  241. SUNXI_DMA_BASE + SUNXI_DMA_DEST_START_ADDRR_REG0);
  242. writel(SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC
  243. | SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE,
  244. SUNXI_DMA_BASE + SUNXI_DMA_DDMA_PARA_REG0);
  245. writel(CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE,
  246. SUNXI_DMA_BASE + SUNXI_DMA_DDMA_BC_REG0); /* 1kB */
  247. writel(SUNXI_DMA_DDMA_CFG_REG_LOADING
  248. | SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32
  249. | SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32
  250. | SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO
  251. | SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC,
  252. SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0);
  253. writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET)
  254. | (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET)
  255. | (NFC_CMD_READSTART | NFC_READ_CMD_OFFSET), SUNXI_NFC_BASE
  256. + NFC_RCMD_SET);
  257. writel(1, SUNXI_NFC_BASE + NFC_SECTOR_NUM);
  258. writel(((page & 0xFFFF) << 16) | column,
  259. SUNXI_NFC_BASE + NFC_ADDR_LOW);
  260. writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
  261. writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_DATA_TRANS |
  262. NFC_PAGE_CMD | NFC_WAIT_FLAG | (4 << NFC_ADDR_NUM_OFFSET) |
  263. NFC_SEND_ADR | NFC_DATA_SWAP_METHOD | (syndrome ? NFC_SEQ : 0),
  264. SUNXI_NFC_BASE + NFC_CMD);
  265. if (!check_value(SUNXI_NFC_BASE + NFC_ST, (1 << 2),
  266. MAX_RETRIES)) {
  267. printf("Error while initializing dma interrupt\n");
  268. return;
  269. }
  270. if (!check_value_negated(SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0,
  271. SUNXI_DMA_DDMA_CFG_REG_LOADING, MAX_RETRIES)) {
  272. printf("Error while waiting for dma transfer to finish\n");
  273. return;
  274. }
  275. if (readl(SUNXI_NFC_BASE + NFC_ECC_ST))
  276. (*ecc_errors)++;
  277. }
  278. int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
  279. {
  280. void *current_dest;
  281. uint32_t count;
  282. uint32_t current_count;
  283. uint32_t ecc_errors = 0;
  284. memset(dest, 0x0, size); /* clean destination memory */
  285. for (current_dest = dest;
  286. current_dest < (dest + size);
  287. current_dest += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE) {
  288. nand_read_page(offs, offs
  289. < CONFIG_NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END,
  290. &ecc_errors);
  291. count = current_dest - dest;
  292. if (size - count > CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
  293. current_count = CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
  294. else
  295. current_count = size - count;
  296. memcpy(current_dest,
  297. temp_buf,
  298. current_count);
  299. offs += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
  300. }
  301. return ecc_errors ? -1 : 0;
  302. }
  303. void nand_deselect(void) {}