ohci-hcd.c 52 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
  3. *
  4. * Interrupt support is added. Now, it has been tested
  5. * on ULI1575 chip and works well with USB keyboard.
  6. *
  7. * (C) Copyright 2007
  8. * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
  9. *
  10. * (C) Copyright 2003
  11. * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
  12. *
  13. * Note: Much of this code has been derived from Linux 2.4
  14. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  15. * (C) Copyright 2000-2002 David Brownell
  16. *
  17. * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
  18. * ebenard@eukrea.com - based on s3c24x0's driver
  19. *
  20. * See file CREDITS for list of people who contributed to this
  21. * project.
  22. *
  23. * This program is free software; you can redistribute it and/or
  24. * modify it under the terms of the GNU General Public License as
  25. * published by the Free Software Foundation; either version 2 of
  26. * the License, or (at your option) any later version.
  27. *
  28. * This program is distributed in the hope that it will be useful,
  29. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  30. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  31. * GNU General Public License for more details.
  32. *
  33. * You should have received a copy of the GNU General Public License
  34. * along with this program; if not, write to the Free Software
  35. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  36. * MA 02111-1307 USA
  37. *
  38. */
  39. /*
  40. * IMPORTANT NOTES
  41. * 1 - Read doc/README.generic_usb_ohci
  42. * 2 - this driver is intended for use with USB Mass Storage Devices
  43. * (BBB) and USB keyboard. There is NO support for Isochronous pipes!
  44. * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
  45. * to activate workaround for bug #41 or this driver will NOT work!
  46. */
  47. #include <common.h>
  48. #include <asm/byteorder.h>
  49. #if defined(CONFIG_PCI_OHCI)
  50. # include <pci.h>
  51. #if !defined(CONFIG_PCI_OHCI_DEVNO)
  52. #define CONFIG_PCI_OHCI_DEVNO 0
  53. #endif
  54. #endif
  55. #include <malloc.h>
  56. #include <usb.h>
  57. #include "ohci.h"
  58. #ifdef CONFIG_AT91RM9200
  59. #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
  60. #endif
  61. #if defined(CONFIG_ARM920T) || \
  62. defined(CONFIG_S3C24X0) || \
  63. defined(CONFIG_S3C6400) || \
  64. defined(CONFIG_440EP) || \
  65. defined(CONFIG_PCI_OHCI) || \
  66. defined(CONFIG_MPC5200) || \
  67. defined(CONFIG_SYS_OHCI_USE_NPS)
  68. # define OHCI_USE_NPS /* force NoPowerSwitching mode */
  69. #endif
  70. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  71. #undef DEBUG
  72. #undef SHOW_INFO
  73. #undef OHCI_FILL_TRACE
  74. /* For initializing controller (mask in an HCFS mode too) */
  75. #define OHCI_CONTROL_INIT \
  76. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  77. /*
  78. * e.g. PCI controllers need this
  79. */
  80. #ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
  81. # define readl(a) __swap_32(*((volatile u32 *)(a)))
  82. # define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
  83. #else
  84. # define readl(a) (*((volatile u32 *)(a)))
  85. # define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
  86. #endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
  87. #define min_t(type, x, y) \
  88. ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
  89. #ifdef CONFIG_PCI_OHCI
  90. static struct pci_device_id ohci_pci_ids[] = {
  91. {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
  92. {0x1033, 0x0035}, /* NEC PCI OHCI module ids */
  93. {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */
  94. /* Please add supported PCI OHCI controller ids here */
  95. {0, 0}
  96. };
  97. #endif
  98. #ifdef CONFIG_PCI_EHCI_DEVNO
  99. static struct pci_device_id ehci_pci_ids[] = {
  100. {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */
  101. /* Please add supported PCI EHCI controller ids here */
  102. {0, 0}
  103. };
  104. #endif
  105. #ifdef DEBUG
  106. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  107. #else
  108. #define dbg(format, arg...) do {} while (0)
  109. #endif /* DEBUG */
  110. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  111. #ifdef SHOW_INFO
  112. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  113. #else
  114. #define info(format, arg...) do {} while (0)
  115. #endif
  116. #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER
  117. # define m16_swap(x) cpu_to_be16(x)
  118. # define m32_swap(x) cpu_to_be32(x)
  119. #else
  120. # define m16_swap(x) cpu_to_le16(x)
  121. # define m32_swap(x) cpu_to_le32(x)
  122. #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */
  123. /* global ohci_t */
  124. static ohci_t gohci;
  125. /* this must be aligned to a 256 byte boundary */
  126. struct ohci_hcca ghcca[1];
  127. /* a pointer to the aligned storage */
  128. struct ohci_hcca *phcca;
  129. /* this allocates EDs for all possible endpoints */
  130. struct ohci_device ohci_dev;
  131. /* device which was disconnected */
  132. struct usb_device *devgone;
  133. static inline u32 roothub_a(struct ohci *hc)
  134. { return readl(&hc->regs->roothub.a); }
  135. static inline u32 roothub_b(struct ohci *hc)
  136. { return readl(&hc->regs->roothub.b); }
  137. static inline u32 roothub_status(struct ohci *hc)
  138. { return readl(&hc->regs->roothub.status); }
  139. static inline u32 roothub_portstatus(struct ohci *hc, int i)
  140. { return readl(&hc->regs->roothub.portstatus[i]); }
  141. /* forward declaration */
  142. static int hc_interrupt(void);
  143. static void td_submit_job(struct usb_device *dev, unsigned long pipe,
  144. void *buffer, int transfer_len,
  145. struct devrequest *setup, urb_priv_t *urb,
  146. int interval);
  147. /*-------------------------------------------------------------------------*
  148. * URB support functions
  149. *-------------------------------------------------------------------------*/
  150. /* free HCD-private data associated with this URB */
  151. static void urb_free_priv(urb_priv_t *urb)
  152. {
  153. int i;
  154. int last;
  155. struct td *td;
  156. last = urb->length - 1;
  157. if (last >= 0) {
  158. for (i = 0; i <= last; i++) {
  159. td = urb->td[i];
  160. if (td) {
  161. td->usb_dev = NULL;
  162. urb->td[i] = NULL;
  163. }
  164. }
  165. }
  166. free(urb);
  167. }
  168. /*-------------------------------------------------------------------------*/
  169. #ifdef DEBUG
  170. static int sohci_get_current_frame_number(struct usb_device *dev);
  171. /* debug| print the main components of an URB
  172. * small: 0) header + data packets 1) just header */
  173. static void pkt_print(urb_priv_t *purb, struct usb_device *dev,
  174. unsigned long pipe, void *buffer, int transfer_len,
  175. struct devrequest *setup, char *str, int small)
  176. {
  177. dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx",
  178. str,
  179. sohci_get_current_frame_number(dev),
  180. usb_pipedevice(pipe),
  181. usb_pipeendpoint(pipe),
  182. usb_pipeout(pipe)? 'O': 'I',
  183. usb_pipetype(pipe) < 2 ? \
  184. (usb_pipeint(pipe)? "INTR": "ISOC"): \
  185. (usb_pipecontrol(pipe)? "CTRL": "BULK"),
  186. (purb ? purb->actual_length : 0),
  187. transfer_len, dev->status);
  188. #ifdef OHCI_VERBOSE_DEBUG
  189. if (!small) {
  190. int i, len;
  191. if (usb_pipecontrol(pipe)) {
  192. printf(__FILE__ ": cmd(8):");
  193. for (i = 0; i < 8 ; i++)
  194. printf(" %02x", ((__u8 *) setup) [i]);
  195. printf("\n");
  196. }
  197. if (transfer_len > 0 && buffer) {
  198. printf(__FILE__ ": data(%d/%d):",
  199. (purb ? purb->actual_length : 0),
  200. transfer_len);
  201. len = usb_pipeout(pipe)? transfer_len:
  202. (purb ? purb->actual_length : 0);
  203. for (i = 0; i < 16 && i < len; i++)
  204. printf(" %02x", ((__u8 *) buffer) [i]);
  205. printf("%s\n", i < len? "...": "");
  206. }
  207. }
  208. #endif
  209. }
  210. /* just for debugging; prints non-empty branches of the int ed tree
  211. * inclusive iso eds */
  212. void ep_print_int_eds(ohci_t *ohci, char *str)
  213. {
  214. int i, j;
  215. __u32 *ed_p;
  216. for (i = 0; i < 32; i++) {
  217. j = 5;
  218. ed_p = &(ohci->hcca->int_table [i]);
  219. if (*ed_p == 0)
  220. continue;
  221. printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  222. while (*ed_p != 0 && j--) {
  223. ed_t *ed = (ed_t *)m32_swap(ed_p);
  224. printf(" ed: %4x;", ed->hwINFO);
  225. ed_p = &ed->hwNextED;
  226. }
  227. printf("\n");
  228. }
  229. }
  230. static void ohci_dump_intr_mask(char *label, __u32 mask)
  231. {
  232. dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  233. label,
  234. mask,
  235. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  236. (mask & OHCI_INTR_OC) ? " OC" : "",
  237. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  238. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  239. (mask & OHCI_INTR_UE) ? " UE" : "",
  240. (mask & OHCI_INTR_RD) ? " RD" : "",
  241. (mask & OHCI_INTR_SF) ? " SF" : "",
  242. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  243. (mask & OHCI_INTR_SO) ? " SO" : ""
  244. );
  245. }
  246. static void maybe_print_eds(char *label, __u32 value)
  247. {
  248. ed_t *edp = (ed_t *)value;
  249. if (value) {
  250. dbg("%s %08x", label, value);
  251. dbg("%08x", edp->hwINFO);
  252. dbg("%08x", edp->hwTailP);
  253. dbg("%08x", edp->hwHeadP);
  254. dbg("%08x", edp->hwNextED);
  255. }
  256. }
  257. static char *hcfs2string(int state)
  258. {
  259. switch (state) {
  260. case OHCI_USB_RESET: return "reset";
  261. case OHCI_USB_RESUME: return "resume";
  262. case OHCI_USB_OPER: return "operational";
  263. case OHCI_USB_SUSPEND: return "suspend";
  264. }
  265. return "?";
  266. }
  267. /* dump control and status registers */
  268. static void ohci_dump_status(ohci_t *controller)
  269. {
  270. struct ohci_regs *regs = controller->regs;
  271. __u32 temp;
  272. temp = readl(&regs->revision) & 0xff;
  273. if (temp != 0x10)
  274. dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
  275. temp = readl(&regs->control);
  276. dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  277. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  278. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  279. (temp & OHCI_CTRL_IR) ? " IR" : "",
  280. hcfs2string(temp & OHCI_CTRL_HCFS),
  281. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  282. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  283. (temp & OHCI_CTRL_IE) ? " IE" : "",
  284. (temp & OHCI_CTRL_PLE) ? " PLE" : "",
  285. temp & OHCI_CTRL_CBSR
  286. );
  287. temp = readl(&regs->cmdstatus);
  288. dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  289. (temp & OHCI_SOC) >> 16,
  290. (temp & OHCI_OCR) ? " OCR" : "",
  291. (temp & OHCI_BLF) ? " BLF" : "",
  292. (temp & OHCI_CLF) ? " CLF" : "",
  293. (temp & OHCI_HCR) ? " HCR" : ""
  294. );
  295. ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
  296. ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
  297. maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent));
  298. maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead));
  299. maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent));
  300. maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead));
  301. maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent));
  302. maybe_print_eds("donehead", readl(&regs->donehead));
  303. }
  304. static void ohci_dump_roothub(ohci_t *controller, int verbose)
  305. {
  306. __u32 temp, ndp, i;
  307. temp = roothub_a(controller);
  308. ndp = (temp & RH_A_NDP);
  309. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  310. ndp = (ndp == 2) ? 1:0;
  311. #endif
  312. if (verbose) {
  313. dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  314. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  315. (temp & RH_A_NOCP) ? " NOCP" : "",
  316. (temp & RH_A_OCPM) ? " OCPM" : "",
  317. (temp & RH_A_DT) ? " DT" : "",
  318. (temp & RH_A_NPS) ? " NPS" : "",
  319. (temp & RH_A_PSM) ? " PSM" : "",
  320. ndp
  321. );
  322. temp = roothub_b(controller);
  323. dbg("roothub.b: %08x PPCM=%04x DR=%04x",
  324. temp,
  325. (temp & RH_B_PPCM) >> 16,
  326. (temp & RH_B_DR)
  327. );
  328. temp = roothub_status(controller);
  329. dbg("roothub.status: %08x%s%s%s%s%s%s",
  330. temp,
  331. (temp & RH_HS_CRWE) ? " CRWE" : "",
  332. (temp & RH_HS_OCIC) ? " OCIC" : "",
  333. (temp & RH_HS_LPSC) ? " LPSC" : "",
  334. (temp & RH_HS_DRWE) ? " DRWE" : "",
  335. (temp & RH_HS_OCI) ? " OCI" : "",
  336. (temp & RH_HS_LPS) ? " LPS" : ""
  337. );
  338. }
  339. for (i = 0; i < ndp; i++) {
  340. temp = roothub_portstatus(controller, i);
  341. dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  342. i,
  343. temp,
  344. (temp & RH_PS_PRSC) ? " PRSC" : "",
  345. (temp & RH_PS_OCIC) ? " OCIC" : "",
  346. (temp & RH_PS_PSSC) ? " PSSC" : "",
  347. (temp & RH_PS_PESC) ? " PESC" : "",
  348. (temp & RH_PS_CSC) ? " CSC" : "",
  349. (temp & RH_PS_LSDA) ? " LSDA" : "",
  350. (temp & RH_PS_PPS) ? " PPS" : "",
  351. (temp & RH_PS_PRS) ? " PRS" : "",
  352. (temp & RH_PS_POCI) ? " POCI" : "",
  353. (temp & RH_PS_PSS) ? " PSS" : "",
  354. (temp & RH_PS_PES) ? " PES" : "",
  355. (temp & RH_PS_CCS) ? " CCS" : ""
  356. );
  357. }
  358. }
  359. static void ohci_dump(ohci_t *controller, int verbose)
  360. {
  361. dbg("OHCI controller usb-%s state", controller->slot_name);
  362. /* dumps some of the state we know about */
  363. ohci_dump_status(controller);
  364. if (verbose)
  365. ep_print_int_eds(controller, "hcca");
  366. dbg("hcca frame #%04x", controller->hcca->frame_no);
  367. ohci_dump_roothub(controller, 1);
  368. }
  369. #endif /* DEBUG */
  370. /*-------------------------------------------------------------------------*
  371. * Interface functions (URB)
  372. *-------------------------------------------------------------------------*/
  373. /* get a transfer request */
  374. int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup)
  375. {
  376. ohci_t *ohci;
  377. ed_t *ed;
  378. urb_priv_t *purb_priv = urb;
  379. int i, size = 0;
  380. struct usb_device *dev = urb->dev;
  381. unsigned long pipe = urb->pipe;
  382. void *buffer = urb->transfer_buffer;
  383. int transfer_len = urb->transfer_buffer_length;
  384. int interval = urb->interval;
  385. ohci = &gohci;
  386. /* when controller's hung, permit only roothub cleanup attempts
  387. * such as powering down ports */
  388. if (ohci->disabled) {
  389. err("sohci_submit_job: EPIPE");
  390. return -1;
  391. }
  392. /* we're about to begin a new transaction here so mark the
  393. * URB unfinished */
  394. urb->finished = 0;
  395. /* every endpoint has a ed, locate and fill it */
  396. ed = ep_add_ed(dev, pipe, interval, 1);
  397. if (!ed) {
  398. err("sohci_submit_job: ENOMEM");
  399. return -1;
  400. }
  401. /* for the private part of the URB we need the number of TDs (size) */
  402. switch (usb_pipetype(pipe)) {
  403. case PIPE_BULK: /* one TD for every 4096 Byte */
  404. size = (transfer_len - 1) / 4096 + 1;
  405. break;
  406. case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  407. size = (transfer_len == 0)? 2:
  408. (transfer_len - 1) / 4096 + 3;
  409. break;
  410. case PIPE_INTERRUPT: /* 1 TD */
  411. size = 1;
  412. break;
  413. }
  414. ed->purb = urb;
  415. if (size >= (N_URB_TD - 1)) {
  416. err("need %d TDs, only have %d", size, N_URB_TD);
  417. return -1;
  418. }
  419. purb_priv->pipe = pipe;
  420. /* fill the private part of the URB */
  421. purb_priv->length = size;
  422. purb_priv->ed = ed;
  423. purb_priv->actual_length = 0;
  424. /* allocate the TDs */
  425. /* note that td[0] was allocated in ep_add_ed */
  426. for (i = 0; i < size; i++) {
  427. purb_priv->td[i] = td_alloc(dev);
  428. if (!purb_priv->td[i]) {
  429. purb_priv->length = i;
  430. urb_free_priv(purb_priv);
  431. err("sohci_submit_job: ENOMEM");
  432. return -1;
  433. }
  434. }
  435. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  436. urb_free_priv(purb_priv);
  437. err("sohci_submit_job: EINVAL");
  438. return -1;
  439. }
  440. /* link the ed into a chain if is not already */
  441. if (ed->state != ED_OPER)
  442. ep_link(ohci, ed);
  443. /* fill the TDs and link it to the ed */
  444. td_submit_job(dev, pipe, buffer, transfer_len,
  445. setup, purb_priv, interval);
  446. return 0;
  447. }
  448. static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)
  449. {
  450. struct ohci_regs *regs = hc->regs;
  451. switch (usb_pipetype(urb->pipe)) {
  452. case PIPE_INTERRUPT:
  453. /* implicitly requeued */
  454. if (urb->dev->irq_handle &&
  455. (urb->dev->irq_act_len = urb->actual_length)) {
  456. writel(OHCI_INTR_WDH, &regs->intrenable);
  457. readl(&regs->intrenable); /* PCI posting flush */
  458. urb->dev->irq_handle(urb->dev);
  459. writel(OHCI_INTR_WDH, &regs->intrdisable);
  460. readl(&regs->intrdisable); /* PCI posting flush */
  461. }
  462. urb->actual_length = 0;
  463. td_submit_job(
  464. urb->dev,
  465. urb->pipe,
  466. urb->transfer_buffer,
  467. urb->transfer_buffer_length,
  468. NULL,
  469. urb,
  470. urb->interval);
  471. break;
  472. case PIPE_CONTROL:
  473. case PIPE_BULK:
  474. break;
  475. default:
  476. return 0;
  477. }
  478. return 1;
  479. }
  480. /*-------------------------------------------------------------------------*/
  481. #ifdef DEBUG
  482. /* tell us the current USB frame number */
  483. static int sohci_get_current_frame_number(struct usb_device *usb_dev)
  484. {
  485. ohci_t *ohci = &gohci;
  486. return m16_swap(ohci->hcca->frame_no);
  487. }
  488. #endif
  489. /*-------------------------------------------------------------------------*
  490. * ED handling functions
  491. *-------------------------------------------------------------------------*/
  492. /* search for the right branch to insert an interrupt ed into the int tree
  493. * do some load ballancing;
  494. * returns the branch and
  495. * sets the interval to interval = 2^integer (ld (interval)) */
  496. static int ep_int_ballance(ohci_t *ohci, int interval, int load)
  497. {
  498. int i, branch = 0;
  499. /* search for the least loaded interrupt endpoint
  500. * branch of all 32 branches
  501. */
  502. for (i = 0; i < 32; i++)
  503. if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
  504. branch = i;
  505. branch = branch % interval;
  506. for (i = branch; i < 32; i += interval)
  507. ohci->ohci_int_load [i] += load;
  508. return branch;
  509. }
  510. /*-------------------------------------------------------------------------*/
  511. /* 2^int( ld (inter)) */
  512. static int ep_2_n_interval(int inter)
  513. {
  514. int i;
  515. for (i = 0; ((inter >> i) > 1) && (i < 5); i++);
  516. return 1 << i;
  517. }
  518. /*-------------------------------------------------------------------------*/
  519. /* the int tree is a binary tree
  520. * in order to process it sequentially the indexes of the branches have to
  521. * be mapped the mapping reverses the bits of a word of num_bits length */
  522. static int ep_rev(int num_bits, int word)
  523. {
  524. int i, wout = 0;
  525. for (i = 0; i < num_bits; i++)
  526. wout |= (((word >> i) & 1) << (num_bits - i - 1));
  527. return wout;
  528. }
  529. /*-------------------------------------------------------------------------*
  530. * ED handling functions
  531. *-------------------------------------------------------------------------*/
  532. /* link an ed into one of the HC chains */
  533. static int ep_link(ohci_t *ohci, ed_t *edi)
  534. {
  535. volatile ed_t *ed = edi;
  536. int int_branch;
  537. int i;
  538. int inter;
  539. int interval;
  540. int load;
  541. __u32 *ed_p;
  542. ed->state = ED_OPER;
  543. ed->int_interval = 0;
  544. switch (ed->type) {
  545. case PIPE_CONTROL:
  546. ed->hwNextED = 0;
  547. if (ohci->ed_controltail == NULL)
  548. writel(ed, &ohci->regs->ed_controlhead);
  549. else
  550. ohci->ed_controltail->hwNextED =
  551. m32_swap((unsigned long)ed);
  552. ed->ed_prev = ohci->ed_controltail;
  553. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  554. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  555. ohci->hc_control |= OHCI_CTRL_CLE;
  556. writel(ohci->hc_control, &ohci->regs->control);
  557. }
  558. ohci->ed_controltail = edi;
  559. break;
  560. case PIPE_BULK:
  561. ed->hwNextED = 0;
  562. if (ohci->ed_bulktail == NULL)
  563. writel(ed, &ohci->regs->ed_bulkhead);
  564. else
  565. ohci->ed_bulktail->hwNextED =
  566. m32_swap((unsigned long)ed);
  567. ed->ed_prev = ohci->ed_bulktail;
  568. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  569. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  570. ohci->hc_control |= OHCI_CTRL_BLE;
  571. writel(ohci->hc_control, &ohci->regs->control);
  572. }
  573. ohci->ed_bulktail = edi;
  574. break;
  575. case PIPE_INTERRUPT:
  576. load = ed->int_load;
  577. interval = ep_2_n_interval(ed->int_period);
  578. ed->int_interval = interval;
  579. int_branch = ep_int_ballance(ohci, interval, load);
  580. ed->int_branch = int_branch;
  581. for (i = 0; i < ep_rev(6, interval); i += inter) {
  582. inter = 1;
  583. for (ed_p = &(ohci->hcca->int_table[\
  584. ep_rev(5, i) + int_branch]);
  585. (*ed_p != 0) &&
  586. (((ed_t *)ed_p)->int_interval >= interval);
  587. ed_p = &(((ed_t *)ed_p)->hwNextED))
  588. inter = ep_rev(6,
  589. ((ed_t *)ed_p)->int_interval);
  590. ed->hwNextED = *ed_p;
  591. *ed_p = m32_swap((unsigned long)ed);
  592. }
  593. break;
  594. }
  595. return 0;
  596. }
  597. /*-------------------------------------------------------------------------*/
  598. /* scan the periodic table to find and unlink this ED */
  599. static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed,
  600. unsigned index, unsigned period)
  601. {
  602. for (; index < NUM_INTS; index += period) {
  603. __u32 *ed_p = &ohci->hcca->int_table [index];
  604. /* ED might have been unlinked through another path */
  605. while (*ed_p != 0) {
  606. if (((struct ed *)
  607. m32_swap((unsigned long)ed_p)) == ed) {
  608. *ed_p = ed->hwNextED;
  609. break;
  610. }
  611. ed_p = &(((struct ed *)
  612. m32_swap((unsigned long)ed_p))->hwNextED);
  613. }
  614. }
  615. }
  616. /* unlink an ed from one of the HC chains.
  617. * just the link to the ed is unlinked.
  618. * the link from the ed still points to another operational ed or 0
  619. * so the HC can eventually finish the processing of the unlinked ed */
  620. static int ep_unlink(ohci_t *ohci, ed_t *edi)
  621. {
  622. volatile ed_t *ed = edi;
  623. int i;
  624. ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
  625. switch (ed->type) {
  626. case PIPE_CONTROL:
  627. if (ed->ed_prev == NULL) {
  628. if (!ed->hwNextED) {
  629. ohci->hc_control &= ~OHCI_CTRL_CLE;
  630. writel(ohci->hc_control, &ohci->regs->control);
  631. }
  632. writel(m32_swap(*((__u32 *)&ed->hwNextED)),
  633. &ohci->regs->ed_controlhead);
  634. } else {
  635. ed->ed_prev->hwNextED = ed->hwNextED;
  636. }
  637. if (ohci->ed_controltail == ed) {
  638. ohci->ed_controltail = ed->ed_prev;
  639. } else {
  640. ((ed_t *)m32_swap(
  641. *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  642. }
  643. break;
  644. case PIPE_BULK:
  645. if (ed->ed_prev == NULL) {
  646. if (!ed->hwNextED) {
  647. ohci->hc_control &= ~OHCI_CTRL_BLE;
  648. writel(ohci->hc_control, &ohci->regs->control);
  649. }
  650. writel(m32_swap(*((__u32 *)&ed->hwNextED)),
  651. &ohci->regs->ed_bulkhead);
  652. } else {
  653. ed->ed_prev->hwNextED = ed->hwNextED;
  654. }
  655. if (ohci->ed_bulktail == ed) {
  656. ohci->ed_bulktail = ed->ed_prev;
  657. } else {
  658. ((ed_t *)m32_swap(
  659. *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  660. }
  661. break;
  662. case PIPE_INTERRUPT:
  663. periodic_unlink(ohci, ed, 0, 1);
  664. for (i = ed->int_branch; i < 32; i += ed->int_interval)
  665. ohci->ohci_int_load[i] -= ed->int_load;
  666. break;
  667. }
  668. ed->state = ED_UNLINK;
  669. return 0;
  670. }
  671. /*-------------------------------------------------------------------------*/
  672. /* add/reinit an endpoint; this should be done once at the
  673. * usb_set_configuration command, but the USB stack is a little bit
  674. * stateless so we do it at every transaction if the state of the ed
  675. * is ED_NEW then a dummy td is added and the state is changed to
  676. * ED_UNLINK in all other cases the state is left unchanged the ed
  677. * info fields are setted anyway even though most of them should not
  678. * change
  679. */
  680. static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe,
  681. int interval, int load)
  682. {
  683. td_t *td;
  684. ed_t *ed_ret;
  685. volatile ed_t *ed;
  686. ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) |
  687. (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))];
  688. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  689. err("ep_add_ed: pending delete");
  690. /* pending delete request */
  691. return NULL;
  692. }
  693. if (ed->state == ED_NEW) {
  694. /* dummy td; end of td list for ed */
  695. td = td_alloc(usb_dev);
  696. ed->hwTailP = m32_swap((unsigned long)td);
  697. ed->hwHeadP = ed->hwTailP;
  698. ed->state = ED_UNLINK;
  699. ed->type = usb_pipetype(pipe);
  700. ohci_dev.ed_cnt++;
  701. }
  702. ed->hwINFO = m32_swap(usb_pipedevice(pipe)
  703. | usb_pipeendpoint(pipe) << 7
  704. | (usb_pipeisoc(pipe)? 0x8000: 0)
  705. | (usb_pipecontrol(pipe)? 0: \
  706. (usb_pipeout(pipe)? 0x800: 0x1000))
  707. | usb_pipeslow(pipe) << 13
  708. | usb_maxpacket(usb_dev, pipe) << 16);
  709. if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
  710. ed->int_period = interval;
  711. ed->int_load = load;
  712. }
  713. return ed_ret;
  714. }
  715. /*-------------------------------------------------------------------------*
  716. * TD handling functions
  717. *-------------------------------------------------------------------------*/
  718. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  719. static void td_fill(ohci_t *ohci, unsigned int info,
  720. void *data, int len,
  721. struct usb_device *dev, int index, urb_priv_t *urb_priv)
  722. {
  723. volatile td_t *td, *td_pt;
  724. #ifdef OHCI_FILL_TRACE
  725. int i;
  726. #endif
  727. if (index > urb_priv->length) {
  728. err("index > length");
  729. return;
  730. }
  731. /* use this td as the next dummy */
  732. td_pt = urb_priv->td [index];
  733. td_pt->hwNextTD = 0;
  734. /* fill the old dummy TD */
  735. td = urb_priv->td [index] =
  736. (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf);
  737. td->ed = urb_priv->ed;
  738. td->next_dl_td = NULL;
  739. td->index = index;
  740. td->data = (__u32)data;
  741. #ifdef OHCI_FILL_TRACE
  742. if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
  743. for (i = 0; i < len; i++)
  744. printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]);
  745. printf("\n");
  746. }
  747. #endif
  748. if (!len)
  749. data = 0;
  750. td->hwINFO = m32_swap(info);
  751. td->hwCBP = m32_swap((unsigned long)data);
  752. if (data)
  753. td->hwBE = m32_swap((unsigned long)(data + len - 1));
  754. else
  755. td->hwBE = 0;
  756. td->hwNextTD = m32_swap((unsigned long)td_pt);
  757. /* append to queue */
  758. td->ed->hwTailP = td->hwNextTD;
  759. }
  760. /*-------------------------------------------------------------------------*/
  761. /* prepare all TDs of a transfer */
  762. static void td_submit_job(struct usb_device *dev, unsigned long pipe,
  763. void *buffer, int transfer_len,
  764. struct devrequest *setup, urb_priv_t *urb,
  765. int interval)
  766. {
  767. ohci_t *ohci = &gohci;
  768. int data_len = transfer_len;
  769. void *data;
  770. int cnt = 0;
  771. __u32 info = 0;
  772. unsigned int toggle = 0;
  773. /* OHCI handles the DATA-toggles itself, we just use the USB-toggle
  774. * bits for reseting */
  775. if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  776. toggle = TD_T_TOGGLE;
  777. } else {
  778. toggle = TD_T_DATA0;
  779. usb_settoggle(dev, usb_pipeendpoint(pipe),
  780. usb_pipeout(pipe), 1);
  781. }
  782. urb->td_cnt = 0;
  783. if (data_len)
  784. data = buffer;
  785. else
  786. data = 0;
  787. switch (usb_pipetype(pipe)) {
  788. case PIPE_BULK:
  789. info = usb_pipeout(pipe)?
  790. TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
  791. while (data_len > 4096) {
  792. td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle),
  793. data, 4096, dev, cnt, urb);
  794. data += 4096; data_len -= 4096; cnt++;
  795. }
  796. info = usb_pipeout(pipe)?
  797. TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
  798. td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data,
  799. data_len, dev, cnt, urb);
  800. cnt++;
  801. if (!ohci->sleeping) {
  802. /* start bulk list */
  803. writel(OHCI_BLF, &ohci->regs->cmdstatus);
  804. }
  805. break;
  806. case PIPE_CONTROL:
  807. /* Setup phase */
  808. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  809. td_fill(ohci, info, setup, 8, dev, cnt++, urb);
  810. /* Optional Data phase */
  811. if (data_len > 0) {
  812. info = usb_pipeout(pipe)?
  813. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
  814. TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
  815. /* NOTE: mishandles transfers >8K, some >4K */
  816. td_fill(ohci, info, data, data_len, dev, cnt++, urb);
  817. }
  818. /* Status phase */
  819. info = usb_pipeout(pipe)?
  820. TD_CC | TD_DP_IN | TD_T_DATA1:
  821. TD_CC | TD_DP_OUT | TD_T_DATA1;
  822. td_fill(ohci, info, data, 0, dev, cnt++, urb);
  823. if (!ohci->sleeping) {
  824. /* start Control list */
  825. writel(OHCI_CLF, &ohci->regs->cmdstatus);
  826. }
  827. break;
  828. case PIPE_INTERRUPT:
  829. info = usb_pipeout(urb->pipe)?
  830. TD_CC | TD_DP_OUT | toggle:
  831. TD_CC | TD_R | TD_DP_IN | toggle;
  832. td_fill(ohci, info, data, data_len, dev, cnt++, urb);
  833. break;
  834. }
  835. if (urb->length != cnt)
  836. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  837. }
  838. /*-------------------------------------------------------------------------*
  839. * Done List handling functions
  840. *-------------------------------------------------------------------------*/
  841. /* calculate the transfer length and update the urb */
  842. static void dl_transfer_length(td_t *td)
  843. {
  844. __u32 tdINFO, tdBE, tdCBP;
  845. urb_priv_t *lurb_priv = td->ed->purb;
  846. tdINFO = m32_swap(td->hwINFO);
  847. tdBE = m32_swap(td->hwBE);
  848. tdCBP = m32_swap(td->hwCBP);
  849. if (!(usb_pipecontrol(lurb_priv->pipe) &&
  850. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  851. if (tdBE != 0) {
  852. if (td->hwCBP == 0)
  853. lurb_priv->actual_length += tdBE - td->data + 1;
  854. else
  855. lurb_priv->actual_length += tdCBP - td->data;
  856. }
  857. }
  858. }
  859. /*-------------------------------------------------------------------------*/
  860. static void check_status(td_t *td_list)
  861. {
  862. urb_priv_t *lurb_priv = td_list->ed->purb;
  863. int urb_len = lurb_priv->length;
  864. __u32 *phwHeadP = &td_list->ed->hwHeadP;
  865. int cc;
  866. cc = TD_CC_GET(m32_swap(td_list->hwINFO));
  867. if (cc) {
  868. err(" USB-error: %s (%x)", cc_to_string[cc], cc);
  869. if (*phwHeadP & m32_swap(0x1)) {
  870. if (lurb_priv &&
  871. ((td_list->index + 1) < urb_len)) {
  872. *phwHeadP =
  873. (lurb_priv->td[urb_len - 1]->hwNextTD &\
  874. m32_swap(0xfffffff0)) |
  875. (*phwHeadP & m32_swap(0x2));
  876. lurb_priv->td_cnt += urb_len -
  877. td_list->index - 1;
  878. } else
  879. *phwHeadP &= m32_swap(0xfffffff2);
  880. }
  881. #ifdef CONFIG_MPC5200
  882. td_list->hwNextTD = 0;
  883. #endif
  884. }
  885. }
  886. /* replies to the request have to be on a FIFO basis so
  887. * we reverse the reversed done-list */
  888. static td_t *dl_reverse_done_list(ohci_t *ohci)
  889. {
  890. __u32 td_list_hc;
  891. td_t *td_rev = NULL;
  892. td_t *td_list = NULL;
  893. td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
  894. ohci->hcca->done_head = 0;
  895. while (td_list_hc) {
  896. td_list = (td_t *)td_list_hc;
  897. check_status(td_list);
  898. td_list->next_dl_td = td_rev;
  899. td_rev = td_list;
  900. td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
  901. }
  902. return td_list;
  903. }
  904. /*-------------------------------------------------------------------------*/
  905. /*-------------------------------------------------------------------------*/
  906. static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status)
  907. {
  908. if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL))
  909. urb->finished = sohci_return_job(ohci, urb);
  910. else
  911. dbg("finish_urb: strange.., ED state %x, \n", status);
  912. }
  913. /*
  914. * Used to take back a TD from the host controller. This would normally be
  915. * called from within dl_done_list, however it may be called directly if the
  916. * HC no longer sees the TD and it has not appeared on the donelist (after
  917. * two frames). This bug has been observed on ZF Micro systems.
  918. */
  919. static int takeback_td(ohci_t *ohci, td_t *td_list)
  920. {
  921. ed_t *ed;
  922. int cc;
  923. int stat = 0;
  924. /* urb_t *urb; */
  925. urb_priv_t *lurb_priv;
  926. __u32 tdINFO, edHeadP, edTailP;
  927. tdINFO = m32_swap(td_list->hwINFO);
  928. ed = td_list->ed;
  929. lurb_priv = ed->purb;
  930. dl_transfer_length(td_list);
  931. lurb_priv->td_cnt++;
  932. /* error code of transfer */
  933. cc = TD_CC_GET(tdINFO);
  934. if (cc) {
  935. err("USB-error: %s (%x)", cc_to_string[cc], cc);
  936. stat = cc_to_error[cc];
  937. }
  938. /* see if this done list makes for all TD's of current URB,
  939. * and mark the URB finished if so */
  940. if (lurb_priv->td_cnt == lurb_priv->length)
  941. finish_urb(ohci, lurb_priv, ed->state);
  942. dbg("dl_done_list: processing TD %x, len %x\n",
  943. lurb_priv->td_cnt, lurb_priv->length);
  944. if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) {
  945. edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
  946. edTailP = m32_swap(ed->hwTailP);
  947. /* unlink eds if they are not busy */
  948. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  949. ep_unlink(ohci, ed);
  950. }
  951. return stat;
  952. }
  953. static int dl_done_list(ohci_t *ohci)
  954. {
  955. int stat = 0;
  956. td_t *td_list = dl_reverse_done_list(ohci);
  957. while (td_list) {
  958. td_t *td_next = td_list->next_dl_td;
  959. stat = takeback_td(ohci, td_list);
  960. td_list = td_next;
  961. }
  962. return stat;
  963. }
  964. /*-------------------------------------------------------------------------*
  965. * Virtual Root Hub
  966. *-------------------------------------------------------------------------*/
  967. /* Device descriptor */
  968. static __u8 root_hub_dev_des[] =
  969. {
  970. 0x12, /* __u8 bLength; */
  971. 0x01, /* __u8 bDescriptorType; Device */
  972. 0x10, /* __u16 bcdUSB; v1.1 */
  973. 0x01,
  974. 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
  975. 0x00, /* __u8 bDeviceSubClass; */
  976. 0x00, /* __u8 bDeviceProtocol; */
  977. 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
  978. 0x00, /* __u16 idVendor; */
  979. 0x00,
  980. 0x00, /* __u16 idProduct; */
  981. 0x00,
  982. 0x00, /* __u16 bcdDevice; */
  983. 0x00,
  984. 0x00, /* __u8 iManufacturer; */
  985. 0x01, /* __u8 iProduct; */
  986. 0x00, /* __u8 iSerialNumber; */
  987. 0x01 /* __u8 bNumConfigurations; */
  988. };
  989. /* Configuration descriptor */
  990. static __u8 root_hub_config_des[] =
  991. {
  992. 0x09, /* __u8 bLength; */
  993. 0x02, /* __u8 bDescriptorType; Configuration */
  994. 0x19, /* __u16 wTotalLength; */
  995. 0x00,
  996. 0x01, /* __u8 bNumInterfaces; */
  997. 0x01, /* __u8 bConfigurationValue; */
  998. 0x00, /* __u8 iConfiguration; */
  999. 0x40, /* __u8 bmAttributes;
  1000. Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
  1001. 0x00, /* __u8 MaxPower; */
  1002. /* interface */
  1003. 0x09, /* __u8 if_bLength; */
  1004. 0x04, /* __u8 if_bDescriptorType; Interface */
  1005. 0x00, /* __u8 if_bInterfaceNumber; */
  1006. 0x00, /* __u8 if_bAlternateSetting; */
  1007. 0x01, /* __u8 if_bNumEndpoints; */
  1008. 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
  1009. 0x00, /* __u8 if_bInterfaceSubClass; */
  1010. 0x00, /* __u8 if_bInterfaceProtocol; */
  1011. 0x00, /* __u8 if_iInterface; */
  1012. /* endpoint */
  1013. 0x07, /* __u8 ep_bLength; */
  1014. 0x05, /* __u8 ep_bDescriptorType; Endpoint */
  1015. 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
  1016. 0x03, /* __u8 ep_bmAttributes; Interrupt */
  1017. 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
  1018. 0x00,
  1019. 0xff /* __u8 ep_bInterval; 255 ms */
  1020. };
  1021. static unsigned char root_hub_str_index0[] =
  1022. {
  1023. 0x04, /* __u8 bLength; */
  1024. 0x03, /* __u8 bDescriptorType; String-descriptor */
  1025. 0x09, /* __u8 lang ID */
  1026. 0x04, /* __u8 lang ID */
  1027. };
  1028. static unsigned char root_hub_str_index1[] =
  1029. {
  1030. 28, /* __u8 bLength; */
  1031. 0x03, /* __u8 bDescriptorType; String-descriptor */
  1032. 'O', /* __u8 Unicode */
  1033. 0, /* __u8 Unicode */
  1034. 'H', /* __u8 Unicode */
  1035. 0, /* __u8 Unicode */
  1036. 'C', /* __u8 Unicode */
  1037. 0, /* __u8 Unicode */
  1038. 'I', /* __u8 Unicode */
  1039. 0, /* __u8 Unicode */
  1040. ' ', /* __u8 Unicode */
  1041. 0, /* __u8 Unicode */
  1042. 'R', /* __u8 Unicode */
  1043. 0, /* __u8 Unicode */
  1044. 'o', /* __u8 Unicode */
  1045. 0, /* __u8 Unicode */
  1046. 'o', /* __u8 Unicode */
  1047. 0, /* __u8 Unicode */
  1048. 't', /* __u8 Unicode */
  1049. 0, /* __u8 Unicode */
  1050. ' ', /* __u8 Unicode */
  1051. 0, /* __u8 Unicode */
  1052. 'H', /* __u8 Unicode */
  1053. 0, /* __u8 Unicode */
  1054. 'u', /* __u8 Unicode */
  1055. 0, /* __u8 Unicode */
  1056. 'b', /* __u8 Unicode */
  1057. 0, /* __u8 Unicode */
  1058. };
  1059. /* Hub class-specific descriptor is constructed dynamically */
  1060. /*-------------------------------------------------------------------------*/
  1061. #define OK(x) len = (x); break
  1062. #ifdef DEBUG
  1063. #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); writel((x), \
  1064. &gohci.regs->roothub.status); }
  1065. #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \
  1066. (x)); writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); }
  1067. #else
  1068. #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
  1069. #define WR_RH_PORTSTAT(x) writel((x), \
  1070. &gohci.regs->roothub.portstatus[wIndex-1])
  1071. #endif
  1072. #define RD_RH_STAT roothub_status(&gohci)
  1073. #define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1)
  1074. /* request to virtual root hub */
  1075. int rh_check_port_status(ohci_t *controller)
  1076. {
  1077. __u32 temp, ndp, i;
  1078. int res;
  1079. res = -1;
  1080. temp = roothub_a(controller);
  1081. ndp = (temp & RH_A_NDP);
  1082. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  1083. ndp = (ndp == 2) ? 1:0;
  1084. #endif
  1085. for (i = 0; i < ndp; i++) {
  1086. temp = roothub_portstatus(controller, i);
  1087. /* check for a device disconnect */
  1088. if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
  1089. (RH_PS_PESC | RH_PS_CSC)) &&
  1090. ((temp & RH_PS_CCS) == 0)) {
  1091. res = i;
  1092. break;
  1093. }
  1094. }
  1095. return res;
  1096. }
  1097. static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  1098. void *buffer, int transfer_len, struct devrequest *cmd)
  1099. {
  1100. void *data = buffer;
  1101. int leni = transfer_len;
  1102. int len = 0;
  1103. int stat = 0;
  1104. __u32 datab[4];
  1105. __u8 *data_buf = (__u8 *)datab;
  1106. __u16 bmRType_bReq;
  1107. __u16 wValue;
  1108. __u16 wIndex;
  1109. __u16 wLength;
  1110. #ifdef DEBUG
  1111. pkt_print(NULL, dev, pipe, buffer, transfer_len,
  1112. cmd, "SUB(rh)", usb_pipein(pipe));
  1113. #else
  1114. wait_ms(1);
  1115. #endif
  1116. if (usb_pipeint(pipe)) {
  1117. info("Root-Hub submit IRQ: NOT implemented");
  1118. return 0;
  1119. }
  1120. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  1121. wValue = le16_to_cpu(cmd->value);
  1122. wIndex = le16_to_cpu(cmd->index);
  1123. wLength = le16_to_cpu(cmd->length);
  1124. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  1125. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  1126. switch (bmRType_bReq) {
  1127. /* Request Destination:
  1128. without flags: Device,
  1129. RH_INTERFACE: interface,
  1130. RH_ENDPOINT: endpoint,
  1131. RH_CLASS means HUB here,
  1132. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  1133. */
  1134. case RH_GET_STATUS:
  1135. *(__u16 *) data_buf = cpu_to_le16(1);
  1136. OK(2);
  1137. case RH_GET_STATUS | RH_INTERFACE:
  1138. *(__u16 *) data_buf = cpu_to_le16(0);
  1139. OK(2);
  1140. case RH_GET_STATUS | RH_ENDPOINT:
  1141. *(__u16 *) data_buf = cpu_to_le16(0);
  1142. OK(2);
  1143. case RH_GET_STATUS | RH_CLASS:
  1144. *(__u32 *) data_buf = cpu_to_le32(
  1145. RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  1146. OK(4);
  1147. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  1148. *(__u32 *) data_buf = cpu_to_le32(RD_RH_PORTSTAT);
  1149. OK(4);
  1150. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  1151. switch (wValue) {
  1152. case (RH_ENDPOINT_STALL):
  1153. OK(0);
  1154. }
  1155. break;
  1156. case RH_CLEAR_FEATURE | RH_CLASS:
  1157. switch (wValue) {
  1158. case RH_C_HUB_LOCAL_POWER:
  1159. OK(0);
  1160. case (RH_C_HUB_OVER_CURRENT):
  1161. WR_RH_STAT(RH_HS_OCIC);
  1162. OK(0);
  1163. }
  1164. break;
  1165. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  1166. switch (wValue) {
  1167. case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0);
  1168. case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0);
  1169. case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0);
  1170. case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0);
  1171. case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0);
  1172. case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0);
  1173. case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0);
  1174. case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0);
  1175. }
  1176. break;
  1177. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  1178. switch (wValue) {
  1179. case (RH_PORT_SUSPEND):
  1180. WR_RH_PORTSTAT(RH_PS_PSS); OK(0);
  1181. case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
  1182. if (RD_RH_PORTSTAT & RH_PS_CCS)
  1183. WR_RH_PORTSTAT(RH_PS_PRS);
  1184. OK(0);
  1185. case (RH_PORT_POWER):
  1186. WR_RH_PORTSTAT(RH_PS_PPS);
  1187. wait_ms(100);
  1188. OK(0);
  1189. case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
  1190. if (RD_RH_PORTSTAT & RH_PS_CCS)
  1191. WR_RH_PORTSTAT(RH_PS_PES);
  1192. OK(0);
  1193. }
  1194. break;
  1195. case RH_SET_ADDRESS:
  1196. gohci.rh.devnum = wValue;
  1197. OK(0);
  1198. case RH_GET_DESCRIPTOR:
  1199. switch ((wValue & 0xff00) >> 8) {
  1200. case (0x01): /* device descriptor */
  1201. len = min_t(unsigned int,
  1202. leni,
  1203. min_t(unsigned int,
  1204. sizeof(root_hub_dev_des),
  1205. wLength));
  1206. data_buf = root_hub_dev_des; OK(len);
  1207. case (0x02): /* configuration descriptor */
  1208. len = min_t(unsigned int,
  1209. leni,
  1210. min_t(unsigned int,
  1211. sizeof(root_hub_config_des),
  1212. wLength));
  1213. data_buf = root_hub_config_des; OK(len);
  1214. case (0x03): /* string descriptors */
  1215. if (wValue == 0x0300) {
  1216. len = min_t(unsigned int,
  1217. leni,
  1218. min_t(unsigned int,
  1219. sizeof(root_hub_str_index0),
  1220. wLength));
  1221. data_buf = root_hub_str_index0;
  1222. OK(len);
  1223. }
  1224. if (wValue == 0x0301) {
  1225. len = min_t(unsigned int,
  1226. leni,
  1227. min_t(unsigned int,
  1228. sizeof(root_hub_str_index1),
  1229. wLength));
  1230. data_buf = root_hub_str_index1;
  1231. OK(len);
  1232. }
  1233. default:
  1234. stat = USB_ST_STALLED;
  1235. }
  1236. break;
  1237. case RH_GET_DESCRIPTOR | RH_CLASS:
  1238. {
  1239. __u32 temp = roothub_a(&gohci);
  1240. data_buf [0] = 9; /* min length; */
  1241. data_buf [1] = 0x29;
  1242. data_buf [2] = temp & RH_A_NDP;
  1243. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  1244. data_buf [2] = (data_buf [2] == 2) ? 1:0;
  1245. #endif
  1246. data_buf [3] = 0;
  1247. if (temp & RH_A_PSM) /* per-port power switching? */
  1248. data_buf [3] |= 0x1;
  1249. if (temp & RH_A_NOCP) /* no overcurrent reporting? */
  1250. data_buf [3] |= 0x10;
  1251. else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */
  1252. data_buf [3] |= 0x8;
  1253. /* corresponds to data_buf[4-7] */
  1254. datab [1] = 0;
  1255. data_buf [5] = (temp & RH_A_POTPGT) >> 24;
  1256. temp = roothub_b(&gohci);
  1257. data_buf [7] = temp & RH_B_DR;
  1258. if (data_buf [2] < 7) {
  1259. data_buf [8] = 0xff;
  1260. } else {
  1261. data_buf [0] += 2;
  1262. data_buf [8] = (temp & RH_B_DR) >> 8;
  1263. data_buf [10] = data_buf [9] = 0xff;
  1264. }
  1265. len = min_t(unsigned int, leni,
  1266. min_t(unsigned int, data_buf [0], wLength));
  1267. OK(len);
  1268. }
  1269. case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK(1);
  1270. case RH_SET_CONFIGURATION: WR_RH_STAT(0x10000); OK(0);
  1271. default:
  1272. dbg("unsupported root hub command");
  1273. stat = USB_ST_STALLED;
  1274. }
  1275. #ifdef DEBUG
  1276. ohci_dump_roothub(&gohci, 1);
  1277. #else
  1278. wait_ms(1);
  1279. #endif
  1280. len = min_t(int, len, leni);
  1281. if (data != data_buf)
  1282. memcpy(data, data_buf, len);
  1283. dev->act_len = len;
  1284. dev->status = stat;
  1285. #ifdef DEBUG
  1286. pkt_print(NULL, dev, pipe, buffer,
  1287. transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
  1288. #else
  1289. wait_ms(1);
  1290. #endif
  1291. return stat;
  1292. }
  1293. /*-------------------------------------------------------------------------*/
  1294. /* common code for handling submit messages - used for all but root hub */
  1295. /* accesses. */
  1296. int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1297. int transfer_len, struct devrequest *setup, int interval)
  1298. {
  1299. int stat = 0;
  1300. int maxsize = usb_maxpacket(dev, pipe);
  1301. int timeout;
  1302. urb_priv_t *urb;
  1303. urb = malloc(sizeof(urb_priv_t));
  1304. memset(urb, 0, sizeof(urb_priv_t));
  1305. urb->dev = dev;
  1306. urb->pipe = pipe;
  1307. urb->transfer_buffer = buffer;
  1308. urb->transfer_buffer_length = transfer_len;
  1309. urb->interval = interval;
  1310. /* device pulled? Shortcut the action. */
  1311. if (devgone == dev) {
  1312. dev->status = USB_ST_CRC_ERR;
  1313. return 0;
  1314. }
  1315. #ifdef DEBUG
  1316. urb->actual_length = 0;
  1317. pkt_print(urb, dev, pipe, buffer, transfer_len,
  1318. setup, "SUB", usb_pipein(pipe));
  1319. #else
  1320. wait_ms(1);
  1321. #endif
  1322. if (!maxsize) {
  1323. err("submit_common_message: pipesize for pipe %lx is zero",
  1324. pipe);
  1325. return -1;
  1326. }
  1327. if (sohci_submit_job(urb, setup) < 0) {
  1328. err("sohci_submit_job failed");
  1329. return -1;
  1330. }
  1331. #if 0
  1332. wait_ms(10);
  1333. /* ohci_dump_status(&gohci); */
  1334. #endif
  1335. /* allow more time for a BULK device to react - some are slow */
  1336. #define BULK_TO 5000 /* timeout in milliseconds */
  1337. if (usb_pipebulk(pipe))
  1338. timeout = BULK_TO;
  1339. else
  1340. timeout = 100;
  1341. /* wait for it to complete */
  1342. for (;;) {
  1343. /* check whether the controller is done */
  1344. stat = hc_interrupt();
  1345. if (stat < 0) {
  1346. stat = USB_ST_CRC_ERR;
  1347. break;
  1348. }
  1349. /* NOTE: since we are not interrupt driven in U-Boot and always
  1350. * handle only one URB at a time, we cannot assume the
  1351. * transaction finished on the first successful return from
  1352. * hc_interrupt().. unless the flag for current URB is set,
  1353. * meaning that all TD's to/from device got actually
  1354. * transferred and processed. If the current URB is not
  1355. * finished we need to re-iterate this loop so as
  1356. * hc_interrupt() gets called again as there needs to be some
  1357. * more TD's to process still */
  1358. if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
  1359. /* 0xff is returned for an SF-interrupt */
  1360. break;
  1361. }
  1362. if (--timeout) {
  1363. wait_ms(1);
  1364. if (!urb->finished)
  1365. dbg("*");
  1366. } else {
  1367. err("CTL:TIMEOUT ");
  1368. dbg("submit_common_msg: TO status %x\n", stat);
  1369. urb->finished = 1;
  1370. stat = USB_ST_CRC_ERR;
  1371. break;
  1372. }
  1373. }
  1374. dev->status = stat;
  1375. dev->act_len = transfer_len;
  1376. #ifdef DEBUG
  1377. pkt_print(urb, dev, pipe, buffer, transfer_len,
  1378. setup, "RET(ctlr)", usb_pipein(pipe));
  1379. #else
  1380. wait_ms(1);
  1381. #endif
  1382. /* free TDs in urb_priv */
  1383. if (!usb_pipeint(pipe))
  1384. urb_free_priv(urb);
  1385. return 0;
  1386. }
  1387. /* submit routines called from usb.c */
  1388. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1389. int transfer_len)
  1390. {
  1391. info("submit_bulk_msg");
  1392. return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
  1393. }
  1394. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1395. int transfer_len, struct devrequest *setup)
  1396. {
  1397. int maxsize = usb_maxpacket(dev, pipe);
  1398. info("submit_control_msg");
  1399. #ifdef DEBUG
  1400. pkt_print(NULL, dev, pipe, buffer, transfer_len,
  1401. setup, "SUB", usb_pipein(pipe));
  1402. #else
  1403. wait_ms(1);
  1404. #endif
  1405. if (!maxsize) {
  1406. err("submit_control_message: pipesize for pipe %lx is zero",
  1407. pipe);
  1408. return -1;
  1409. }
  1410. if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
  1411. gohci.rh.dev = dev;
  1412. /* root hub - redirect */
  1413. return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
  1414. setup);
  1415. }
  1416. return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
  1417. }
  1418. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1419. int transfer_len, int interval)
  1420. {
  1421. info("submit_int_msg");
  1422. return submit_common_msg(dev, pipe, buffer, transfer_len, NULL,
  1423. interval);
  1424. }
  1425. /*-------------------------------------------------------------------------*
  1426. * HC functions
  1427. *-------------------------------------------------------------------------*/
  1428. /* reset the HC and BUS */
  1429. static int hc_reset(ohci_t *ohci)
  1430. {
  1431. #ifdef CONFIG_PCI_EHCI_DEVNO
  1432. pci_dev_t pdev;
  1433. #endif
  1434. int timeout = 30;
  1435. int smm_timeout = 50; /* 0,5 sec */
  1436. dbg("%s\n", __FUNCTION__);
  1437. #ifdef CONFIG_PCI_EHCI_DEVNO
  1438. /*
  1439. * Some multi-function controllers (e.g. ISP1562) allow root hub
  1440. * resetting via EHCI registers only.
  1441. */
  1442. pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO);
  1443. if (pdev != -1) {
  1444. u32 base;
  1445. int timeout = 1000;
  1446. pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
  1447. writel(readl(base + EHCI_USBCMD_OFF) | EHCI_USBCMD_HCRESET,
  1448. base + EHCI_USBCMD_OFF);
  1449. while (readl(base + EHCI_USBCMD_OFF) & EHCI_USBCMD_HCRESET) {
  1450. if (timeout-- <= 0) {
  1451. printf("USB RootHub reset timed out!");
  1452. break;
  1453. }
  1454. udelay(1);
  1455. }
  1456. } else
  1457. printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO);
  1458. #endif
  1459. if (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
  1460. /* SMM owns the HC */
  1461. writel(OHCI_OCR, &ohci->regs->cmdstatus);/* request ownership */
  1462. info("USB HC TakeOver from SMM");
  1463. while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
  1464. wait_ms(10);
  1465. if (--smm_timeout == 0) {
  1466. err("USB HC TakeOver failed!");
  1467. return -1;
  1468. }
  1469. }
  1470. }
  1471. /* Disable HC interrupts */
  1472. writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1473. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
  1474. ohci->slot_name,
  1475. readl(&ohci->regs->control));
  1476. /* Reset USB (needed by some controllers) */
  1477. ohci->hc_control = 0;
  1478. writel(ohci->hc_control, &ohci->regs->control);
  1479. /* HC Reset requires max 10 us delay */
  1480. writel(OHCI_HCR, &ohci->regs->cmdstatus);
  1481. while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1482. if (--timeout == 0) {
  1483. err("USB HC reset timed out!");
  1484. return -1;
  1485. }
  1486. udelay(1);
  1487. }
  1488. return 0;
  1489. }
  1490. /*-------------------------------------------------------------------------*/
  1491. /* Start an OHCI controller, set the BUS operational
  1492. * enable interrupts
  1493. * connect the virtual root hub */
  1494. static int hc_start(ohci_t *ohci)
  1495. {
  1496. __u32 mask;
  1497. unsigned int fminterval;
  1498. ohci->disabled = 1;
  1499. /* Tell the controller where the control and bulk lists are
  1500. * The lists are empty now. */
  1501. writel(0, &ohci->regs->ed_controlhead);
  1502. writel(0, &ohci->regs->ed_bulkhead);
  1503. writel((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
  1504. fminterval = 0x2edf;
  1505. writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1506. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1507. writel(fminterval, &ohci->regs->fminterval);
  1508. writel(0x628, &ohci->regs->lsthresh);
  1509. /* start controller operations */
  1510. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1511. ohci->disabled = 0;
  1512. writel(ohci->hc_control, &ohci->regs->control);
  1513. /* disable all interrupts */
  1514. mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
  1515. OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
  1516. OHCI_INTR_OC | OHCI_INTR_MIE);
  1517. writel(mask, &ohci->regs->intrdisable);
  1518. /* clear all interrupts */
  1519. mask &= ~OHCI_INTR_MIE;
  1520. writel(mask, &ohci->regs->intrstatus);
  1521. /* Choose the interrupts we care about now - but w/o MIE */
  1522. mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1523. writel(mask, &ohci->regs->intrenable);
  1524. #ifdef OHCI_USE_NPS
  1525. /* required for AMD-756 and some Mac platforms */
  1526. writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
  1527. &ohci->regs->roothub.a);
  1528. writel(RH_HS_LPSC, &ohci->regs->roothub.status);
  1529. #endif /* OHCI_USE_NPS */
  1530. #define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
  1531. /* POTPGT delay is bits 24-31, in 2 ms units. */
  1532. mdelay((roothub_a(ohci) >> 23) & 0x1fe);
  1533. /* connect the virtual root hub */
  1534. ohci->rh.devnum = 0;
  1535. return 0;
  1536. }
  1537. /*-------------------------------------------------------------------------*/
  1538. /* Poll USB interrupt. */
  1539. void usb_event_poll(void)
  1540. {
  1541. hc_interrupt();
  1542. }
  1543. /* an interrupt happens */
  1544. static int hc_interrupt(void)
  1545. {
  1546. ohci_t *ohci = &gohci;
  1547. struct ohci_regs *regs = ohci->regs;
  1548. int ints;
  1549. int stat = -1;
  1550. if ((ohci->hcca->done_head != 0) &&
  1551. !(m32_swap(ohci->hcca->done_head) & 0x01)) {
  1552. ints = OHCI_INTR_WDH;
  1553. } else {
  1554. ints = readl(&regs->intrstatus);
  1555. if (ints == ~(u32)0) {
  1556. ohci->disabled++;
  1557. err("%s device removed!", ohci->slot_name);
  1558. return -1;
  1559. } else {
  1560. ints &= readl(&regs->intrenable);
  1561. if (ints == 0) {
  1562. dbg("hc_interrupt: returning..\n");
  1563. return 0xff;
  1564. }
  1565. }
  1566. }
  1567. /* dbg("Interrupt: %x frame: %x", ints,
  1568. le16_to_cpu(ohci->hcca->frame_no)); */
  1569. if (ints & OHCI_INTR_RHSC)
  1570. stat = 0xff;
  1571. if (ints & OHCI_INTR_UE) {
  1572. ohci->disabled++;
  1573. err("OHCI Unrecoverable Error, controller usb-%s disabled",
  1574. ohci->slot_name);
  1575. /* e.g. due to PCI Master/Target Abort */
  1576. #ifdef DEBUG
  1577. ohci_dump(ohci, 1);
  1578. #else
  1579. wait_ms(1);
  1580. #endif
  1581. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1582. /* Make some non-interrupt context restart the controller. */
  1583. /* Count and limit the retries though; either hardware or */
  1584. /* software errors can go forever... */
  1585. hc_reset(ohci);
  1586. return -1;
  1587. }
  1588. if (ints & OHCI_INTR_WDH) {
  1589. wait_ms(1);
  1590. writel(OHCI_INTR_WDH, &regs->intrdisable);
  1591. (void)readl(&regs->intrdisable); /* flush */
  1592. stat = dl_done_list(&gohci);
  1593. writel(OHCI_INTR_WDH, &regs->intrenable);
  1594. (void)readl(&regs->intrdisable); /* flush */
  1595. }
  1596. if (ints & OHCI_INTR_SO) {
  1597. dbg("USB Schedule overrun\n");
  1598. writel(OHCI_INTR_SO, &regs->intrenable);
  1599. stat = -1;
  1600. }
  1601. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1602. if (ints & OHCI_INTR_SF) {
  1603. unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
  1604. wait_ms(1);
  1605. writel(OHCI_INTR_SF, &regs->intrdisable);
  1606. if (ohci->ed_rm_list[frame] != NULL)
  1607. writel(OHCI_INTR_SF, &regs->intrenable);
  1608. stat = 0xff;
  1609. }
  1610. writel(ints, &regs->intrstatus);
  1611. return stat;
  1612. }
  1613. /*-------------------------------------------------------------------------*/
  1614. /*-------------------------------------------------------------------------*/
  1615. /* De-allocate all resources.. */
  1616. static void hc_release_ohci(ohci_t *ohci)
  1617. {
  1618. dbg("USB HC release ohci usb-%s", ohci->slot_name);
  1619. if (!ohci->disabled)
  1620. hc_reset(ohci);
  1621. }
  1622. /*-------------------------------------------------------------------------*/
  1623. /*
  1624. * low level initalisation routine, called from usb.c
  1625. */
  1626. static char ohci_inited = 0;
  1627. int usb_lowlevel_init(void)
  1628. {
  1629. #ifdef CONFIG_PCI_OHCI
  1630. pci_dev_t pdev;
  1631. #endif
  1632. #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
  1633. /* cpu dependant init */
  1634. if (usb_cpu_init())
  1635. return -1;
  1636. #endif
  1637. #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
  1638. /* board dependant init */
  1639. if (usb_board_init())
  1640. return -1;
  1641. #endif
  1642. memset(&gohci, 0, sizeof(ohci_t));
  1643. /* align the storage */
  1644. if ((__u32)&ghcca[0] & 0xff) {
  1645. err("HCCA not aligned!!");
  1646. return -1;
  1647. }
  1648. phcca = &ghcca[0];
  1649. info("aligned ghcca %p", phcca);
  1650. memset(&ohci_dev, 0, sizeof(struct ohci_device));
  1651. if ((__u32)&ohci_dev.ed[0] & 0x7) {
  1652. err("EDs not aligned!!");
  1653. return -1;
  1654. }
  1655. memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
  1656. if ((__u32)gtd & 0x7) {
  1657. err("TDs not aligned!!");
  1658. return -1;
  1659. }
  1660. ptd = gtd;
  1661. gohci.hcca = phcca;
  1662. memset(phcca, 0, sizeof(struct ohci_hcca));
  1663. gohci.disabled = 1;
  1664. gohci.sleeping = 0;
  1665. gohci.irq = -1;
  1666. #ifdef CONFIG_PCI_OHCI
  1667. pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO);
  1668. if (pdev != -1) {
  1669. u16 vid, did;
  1670. u32 base;
  1671. pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
  1672. pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
  1673. printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
  1674. vid, did, (pdev >> 16) & 0xff,
  1675. (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
  1676. pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
  1677. printf("OHCI regs address 0x%08x\n", base);
  1678. gohci.regs = (struct ohci_regs *)base;
  1679. } else
  1680. return -1;
  1681. #else
  1682. gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
  1683. #endif
  1684. gohci.flags = 0;
  1685. gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;
  1686. if (hc_reset (&gohci) < 0) {
  1687. hc_release_ohci (&gohci);
  1688. err ("can't reset usb-%s", gohci.slot_name);
  1689. #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
  1690. /* board dependant cleanup */
  1691. usb_board_init_fail();
  1692. #endif
  1693. #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
  1694. /* cpu dependant cleanup */
  1695. usb_cpu_init_fail();
  1696. #endif
  1697. return -1;
  1698. }
  1699. if (hc_start(&gohci) < 0) {
  1700. err("can't start usb-%s", gohci.slot_name);
  1701. hc_release_ohci(&gohci);
  1702. /* Initialization failed */
  1703. #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
  1704. /* board dependant cleanup */
  1705. usb_board_stop();
  1706. #endif
  1707. #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
  1708. /* cpu dependant cleanup */
  1709. usb_cpu_stop();
  1710. #endif
  1711. return -1;
  1712. }
  1713. #ifdef DEBUG
  1714. ohci_dump(&gohci, 1);
  1715. #else
  1716. wait_ms(1);
  1717. #endif
  1718. ohci_inited = 1;
  1719. return 0;
  1720. }
  1721. int usb_lowlevel_stop(void)
  1722. {
  1723. /* this gets called really early - before the controller has */
  1724. /* even been initialized! */
  1725. if (!ohci_inited)
  1726. return 0;
  1727. /* TODO release any interrupts, etc. */
  1728. /* call hc_release_ohci() here ? */
  1729. hc_reset(&gohci);
  1730. #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
  1731. /* board dependant cleanup */
  1732. if (usb_board_stop())
  1733. return -1;
  1734. #endif
  1735. #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
  1736. /* cpu dependant cleanup */
  1737. if (usb_cpu_stop())
  1738. return -1;
  1739. #endif
  1740. /* This driver is no longer initialised. It needs a new low-level
  1741. * init (board/cpu) before it can be used again. */
  1742. ohci_inited = 0;
  1743. return 0;
  1744. }