misc.c 11 KB

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  1. /*
  2. * Copyright (C) 2012 Altera Corporation <www.altera.com>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <errno.h>
  9. #include <fdtdec.h>
  10. #include <libfdt.h>
  11. #include <altera.h>
  12. #include <miiphy.h>
  13. #include <netdev.h>
  14. #include <watchdog.h>
  15. #include <asm/arch/reset_manager.h>
  16. #include <asm/arch/scan_manager.h>
  17. #include <asm/arch/system_manager.h>
  18. #include <asm/arch/dwmmc.h>
  19. #include <asm/arch/nic301.h>
  20. #include <asm/arch/scu.h>
  21. #include <asm/pl310.h>
  22. #include <dt-bindings/reset/altr,rst-mgr.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. static struct pl310_regs *const pl310 =
  25. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  26. static struct socfpga_system_manager *sysmgr_regs =
  27. (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  28. static struct socfpga_reset_manager *reset_manager_base =
  29. (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
  30. static struct nic301_registers *nic301_regs =
  31. (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  32. static struct scu_registers *scu_regs =
  33. (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  34. int dram_init(void)
  35. {
  36. gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  37. return 0;
  38. }
  39. void enable_caches(void)
  40. {
  41. #ifndef CONFIG_SYS_ICACHE_OFF
  42. icache_enable();
  43. #endif
  44. #ifndef CONFIG_SYS_DCACHE_OFF
  45. dcache_enable();
  46. #endif
  47. }
  48. void v7_outer_cache_enable(void)
  49. {
  50. /* disable the L2 cache */
  51. writel(0, &pl310->pl310_ctrl);
  52. /* enable BRESP, instruction and data prefetch, full line of zeroes */
  53. setbits_le32(&pl310->pl310_aux_ctrl,
  54. L310_AUX_CTRL_DATA_PREFETCH_MASK |
  55. L310_AUX_CTRL_INST_PREFETCH_MASK |
  56. L310_SHARED_ATT_OVERRIDE_ENABLE);
  57. }
  58. /*
  59. * DesignWare Ethernet initialization
  60. */
  61. #ifdef CONFIG_ETH_DESIGNWARE
  62. static void dwmac_deassert_reset(const unsigned int of_reset_id)
  63. {
  64. u32 physhift, reset;
  65. if (of_reset_id == EMAC0_RESET) {
  66. physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
  67. reset = SOCFPGA_RESET(EMAC0);
  68. } else if (of_reset_id == EMAC1_RESET) {
  69. physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
  70. reset = SOCFPGA_RESET(EMAC1);
  71. } else {
  72. printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
  73. return;
  74. }
  75. /* Clearing emac0 PHY interface select to 0 */
  76. clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
  77. SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
  78. /* configure to PHY interface select choosed */
  79. setbits_le32(&sysmgr_regs->emacgrp_ctrl,
  80. SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
  81. /* Release the EMAC controller from reset */
  82. socfpga_per_reset(reset, 0);
  83. }
  84. int cpu_eth_init(bd_t *bis)
  85. {
  86. const void *fdt = gd->fdt_blob;
  87. struct fdtdec_phandle_args args;
  88. int nodes[2]; /* Max. two GMACs */
  89. int ret, count;
  90. int i, node;
  91. /* Put both GMACs into RESET state. */
  92. socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
  93. socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
  94. count = fdtdec_find_aliases_for_id(fdt, "ethernet",
  95. COMPAT_ALTERA_SOCFPGA_DWMAC,
  96. nodes, ARRAY_SIZE(nodes));
  97. for (i = 0; i < count; i++) {
  98. node = nodes[i];
  99. if (node <= 0)
  100. continue;
  101. ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
  102. "#reset-cells", 1, 0,
  103. &args);
  104. if (ret || (args.args_count != 1)) {
  105. debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
  106. continue;
  107. }
  108. dwmac_deassert_reset(args.args[0]);
  109. }
  110. return 0;
  111. }
  112. #endif
  113. #ifdef CONFIG_DWMMC
  114. /*
  115. * Initializes MMC controllers.
  116. * to override, implement board_mmc_init()
  117. */
  118. int cpu_mmc_init(bd_t *bis)
  119. {
  120. return socfpga_dwmmc_init(gd->fdt_blob);
  121. }
  122. #endif
  123. struct {
  124. const char *mode;
  125. const char *name;
  126. } bsel_str[] = {
  127. { "rsvd", "Reserved", },
  128. { "fpga", "FPGA (HPS2FPGA Bridge)", },
  129. { "nand", "NAND Flash (1.8V)", },
  130. { "nand", "NAND Flash (3.0V)", },
  131. { "sd", "SD/MMC External Transceiver (1.8V)", },
  132. { "sd", "SD/MMC Internal Transceiver (3.0V)", },
  133. { "qspi", "QSPI Flash (1.8V)", },
  134. { "qspi", "QSPI Flash (3.0V)", },
  135. };
  136. static const struct {
  137. const u16 pn;
  138. const char *name;
  139. const char *var;
  140. } const socfpga_fpga_model[] = {
  141. /* Cyclone V E */
  142. { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
  143. { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
  144. { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
  145. { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
  146. { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
  147. /* Cyclone V GX/GT */
  148. { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
  149. { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
  150. { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
  151. { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
  152. { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
  153. /* Cyclone V SE/SX/ST */
  154. { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
  155. { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
  156. { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
  157. { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
  158. /* Arria V */
  159. { 0x2d03, "Arria V, D5", "av_d5" },
  160. };
  161. static int socfpga_fpga_id(const bool print_id)
  162. {
  163. const u32 altera_mi = 0x6e;
  164. const u32 id = scan_mgr_get_fpga_id();
  165. const u32 lsb = id & 0x00000001;
  166. const u32 mi = (id >> 1) & 0x000007ff;
  167. const u32 pn = (id >> 12) & 0x0000ffff;
  168. const u32 version = (id >> 28) & 0x0000000f;
  169. int i;
  170. if ((mi != altera_mi) || (lsb != 1)) {
  171. printf("FPGA: Not Altera chip ID\n");
  172. return -EINVAL;
  173. }
  174. for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
  175. if (pn == socfpga_fpga_model[i].pn)
  176. break;
  177. if (i == ARRAY_SIZE(socfpga_fpga_model)) {
  178. printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id);
  179. return -EINVAL;
  180. }
  181. if (print_id)
  182. printf("FPGA: Altera %s, version 0x%01x\n",
  183. socfpga_fpga_model[i].name, version);
  184. return i;
  185. }
  186. /*
  187. * Print CPU information
  188. */
  189. #if defined(CONFIG_DISPLAY_CPUINFO)
  190. int print_cpuinfo(void)
  191. {
  192. const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
  193. puts("CPU: Altera SoCFPGA Platform\n");
  194. socfpga_fpga_id(1);
  195. printf("BOOT: %s\n", bsel_str[bsel].name);
  196. return 0;
  197. }
  198. #endif
  199. #ifdef CONFIG_ARCH_MISC_INIT
  200. int arch_misc_init(void)
  201. {
  202. const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
  203. const int fpga_id = socfpga_fpga_id(0);
  204. setenv("bootmode", bsel_str[bsel].mode);
  205. if (fpga_id >= 0)
  206. setenv("fpgatype", socfpga_fpga_model[fpga_id].var);
  207. return 0;
  208. }
  209. #endif
  210. #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
  211. defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
  212. int overwrite_console(void)
  213. {
  214. return 0;
  215. }
  216. #endif
  217. #ifdef CONFIG_FPGA
  218. /*
  219. * FPGA programming support for SoC FPGA Cyclone V
  220. */
  221. static Altera_desc altera_fpga[] = {
  222. {
  223. /* Family */
  224. Altera_SoCFPGA,
  225. /* Interface type */
  226. fast_passive_parallel,
  227. /* No limitation as additional data will be ignored */
  228. -1,
  229. /* No device function table */
  230. NULL,
  231. /* Base interface address specified in driver */
  232. NULL,
  233. /* No cookie implementation */
  234. 0
  235. },
  236. };
  237. /* add device descriptor to FPGA device table */
  238. static void socfpga_fpga_add(void)
  239. {
  240. int i;
  241. fpga_init();
  242. for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
  243. fpga_add(fpga_altera, &altera_fpga[i]);
  244. }
  245. #else
  246. static inline void socfpga_fpga_add(void) {}
  247. #endif
  248. int arch_cpu_init(void)
  249. {
  250. #ifdef CONFIG_HW_WATCHDOG
  251. /*
  252. * In case the watchdog is enabled, make sure to (re-)configure it
  253. * so that the defined timeout is valid. Otherwise the SPL (Perloader)
  254. * timeout value is still active which might too short for Linux
  255. * booting.
  256. */
  257. hw_watchdog_init();
  258. #else
  259. /*
  260. * If the HW watchdog is NOT enabled, make sure it is not running,
  261. * for example because it was enabled in the preloader. This might
  262. * trigger a watchdog-triggered reboot of Linux kernel later.
  263. * Toggle watchdog reset, so watchdog in not running state.
  264. */
  265. socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
  266. socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
  267. #endif
  268. return 0;
  269. }
  270. /*
  271. * Convert all NIC-301 AMBA slaves from secure to non-secure
  272. */
  273. static void socfpga_nic301_slave_ns(void)
  274. {
  275. writel(0x1, &nic301_regs->lwhps2fpgaregs);
  276. writel(0x1, &nic301_regs->hps2fpgaregs);
  277. writel(0x1, &nic301_regs->acp);
  278. writel(0x1, &nic301_regs->rom);
  279. writel(0x1, &nic301_regs->ocram);
  280. writel(0x1, &nic301_regs->sdrdata);
  281. }
  282. static uint32_t iswgrp_handoff[8];
  283. int arch_early_init_r(void)
  284. {
  285. int i;
  286. /*
  287. * Write magic value into magic register to unlock support for
  288. * issuing warm reset. The ancient kernel code expects this
  289. * value to be written into the register by the bootloader, so
  290. * to support that old code, we write it here instead of in the
  291. * reset_cpu() function just before reseting the CPU.
  292. */
  293. writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
  294. for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
  295. iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
  296. socfpga_bridges_reset(1);
  297. socfpga_nic301_slave_ns();
  298. /*
  299. * Private components security:
  300. * U-Boot : configure private timer, global timer and cpu component
  301. * access as non secure for kernel stage (as required by Linux)
  302. */
  303. setbits_le32(&scu_regs->sacr, 0xfff);
  304. /* Configure the L2 controller to make SDRAM start at 0 */
  305. #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  306. writel(0x2, &nic301_regs->remap);
  307. #else
  308. writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
  309. writel(0x1, &pl310->pl310_addr_filter_start);
  310. #endif
  311. /* Add device descriptor to FPGA device table */
  312. socfpga_fpga_add();
  313. #ifdef CONFIG_DESIGNWARE_SPI
  314. /* Get Designware SPI controller out of reset */
  315. socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
  316. socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
  317. #endif
  318. return 0;
  319. }
  320. static void socfpga_sdram_apply_static_cfg(void)
  321. {
  322. const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
  323. const uint32_t applymask = 0x8;
  324. uint32_t val = readl(staticcfg) | applymask;
  325. /*
  326. * SDRAM staticcfg register specific:
  327. * When applying the register setting, the CPU must not access
  328. * SDRAM. Luckily for us, we can abuse i-cache here to help us
  329. * circumvent the SDRAM access issue. The idea is to make sure
  330. * that the code is in one full i-cache line by branching past
  331. * it and back. Once it is in the i-cache, we execute the core
  332. * of the code and apply the register settings.
  333. *
  334. * The code below uses 7 instructions, while the Cortex-A9 has
  335. * 32-byte cachelines, thus the limit is 8 instructions total.
  336. */
  337. asm volatile(
  338. ".align 5 \n"
  339. " b 2f \n"
  340. "1: str %0, [%1] \n"
  341. " dsb \n"
  342. " isb \n"
  343. " b 3f \n"
  344. "2: b 1b \n"
  345. "3: nop \n"
  346. : : "r"(val), "r"(staticcfg) : "memory", "cc");
  347. }
  348. int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  349. {
  350. if (argc != 2)
  351. return CMD_RET_USAGE;
  352. argv++;
  353. switch (*argv[0]) {
  354. case 'e': /* Enable */
  355. writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
  356. socfpga_sdram_apply_static_cfg();
  357. writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
  358. writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
  359. writel(iswgrp_handoff[1], &nic301_regs->remap);
  360. break;
  361. case 'd': /* Disable */
  362. writel(0, &sysmgr_regs->fpgaintfgrp_module);
  363. writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
  364. socfpga_sdram_apply_static_cfg();
  365. writel(0, &reset_manager_base->brg_mod_reset);
  366. writel(1, &nic301_regs->remap);
  367. break;
  368. default:
  369. return CMD_RET_USAGE;
  370. }
  371. return 0;
  372. }
  373. U_BOOT_CMD(
  374. bridge, 2, 1, do_bridge,
  375. "SoCFPGA HPS FPGA bridge control",
  376. "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
  377. "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
  378. ""
  379. );