mrc.c 6.4 KB

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  1. /*
  2. * Copyright (C) 2013, Intel Corporation
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. *
  5. * Ported from Intel released Quark UEFI BIOS
  6. * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
  7. *
  8. * SPDX-License-Identifier: Intel
  9. */
  10. /*
  11. * This is the main Quark Memory Reference Code (MRC)
  12. *
  13. * These functions are generic and should work for any Quark-based board.
  14. *
  15. * MRC requires two data structures to be passed in which are initialized by
  16. * mrc_adjust_params().
  17. *
  18. * The basic flow is as follows:
  19. * 01) Check for supported DDR speed configuration
  20. * 02) Set up Memory Manager buffer as pass-through (POR)
  21. * 03) Set Channel Interleaving Mode and Channel Stride to the most aggressive
  22. * setting possible
  23. * 04) Set up the Memory Controller logic
  24. * 05) Set up the DDR_PHY logic
  25. * 06) Initialise the DRAMs (JEDEC)
  26. * 07) Perform the Receive Enable Calibration algorithm
  27. * 08) Perform the Write Leveling algorithm
  28. * 09) Perform the Read Training algorithm (includes internal Vref)
  29. * 10) Perform the Write Training algorithm
  30. * 11) Set Channel Interleaving Mode and Channel Stride to the desired settings
  31. *
  32. * DRAM unit configuration based on Valleyview MRC.
  33. */
  34. #include <common.h>
  35. #include <version.h>
  36. #include <asm/arch/mrc.h>
  37. #include <asm/arch/msg_port.h>
  38. #include "mrc_util.h"
  39. #include "smc.h"
  40. static const struct mem_init init[] = {
  41. { 0x0101, BM_COLD | BM_FAST | BM_WARM | BM_S3, clear_self_refresh },
  42. { 0x0200, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_ddr_timing_control },
  43. { 0x0103, BM_COLD | BM_FAST , prog_decode_before_jedec },
  44. { 0x0104, BM_COLD | BM_FAST , perform_ddr_reset },
  45. { 0x0300, BM_COLD | BM_FAST | BM_S3, ddrphy_init },
  46. { 0x0400, BM_COLD | BM_FAST , perform_jedec_init },
  47. { 0x0105, BM_COLD | BM_FAST , set_ddr_init_complete },
  48. { 0x0106, BM_FAST | BM_WARM | BM_S3, restore_timings },
  49. { 0x0106, BM_COLD , default_timings },
  50. { 0x0500, BM_COLD , rcvn_cal },
  51. { 0x0600, BM_COLD , wr_level },
  52. { 0x0120, BM_COLD , prog_page_ctrl },
  53. { 0x0700, BM_COLD , rd_train },
  54. { 0x0800, BM_COLD , wr_train },
  55. { 0x010b, BM_COLD , store_timings },
  56. { 0x010c, BM_COLD | BM_FAST | BM_WARM | BM_S3, enable_scrambling },
  57. { 0x010d, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_ddr_control },
  58. { 0x010e, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_dra_drb },
  59. { 0x010f, BM_WARM | BM_S3, perform_wake },
  60. { 0x0110, BM_COLD | BM_FAST | BM_WARM | BM_S3, change_refresh_period },
  61. { 0x0111, BM_COLD | BM_FAST | BM_WARM | BM_S3, set_auto_refresh },
  62. { 0x0112, BM_COLD | BM_FAST | BM_WARM | BM_S3, ecc_enable },
  63. { 0x0113, BM_COLD | BM_FAST , memory_test },
  64. { 0x0114, BM_COLD | BM_FAST | BM_WARM | BM_S3, lock_registers }
  65. };
  66. /* Adjust configuration parameters before initialization sequence */
  67. static void mrc_adjust_params(struct mrc_params *mrc_params)
  68. {
  69. const struct dram_params *dram_params;
  70. uint8_t dram_width;
  71. uint32_t rank_enables;
  72. uint32_t channel_width;
  73. ENTERFN();
  74. /* initially expect success */
  75. mrc_params->status = MRC_SUCCESS;
  76. dram_width = mrc_params->dram_width;
  77. rank_enables = mrc_params->rank_enables;
  78. channel_width = mrc_params->channel_width;
  79. /*
  80. * Setup board layout (must be reviewed as is selecting static timings)
  81. * 0 == R0 (DDR3 x16), 1 == R1 (DDR3 x16),
  82. * 2 == DV (DDR3 x8), 3 == SV (DDR3 x8).
  83. */
  84. if (dram_width == X8)
  85. mrc_params->board_id = 2; /* select x8 layout */
  86. else
  87. mrc_params->board_id = 0; /* select x16 layout */
  88. /* initially no memory */
  89. mrc_params->mem_size = 0;
  90. /* begin of channel settings */
  91. dram_params = &mrc_params->params;
  92. /*
  93. * Determine column bits:
  94. *
  95. * Column: 11 for 8Gbx8, else 10
  96. */
  97. mrc_params->column_bits[0] =
  98. (dram_params[0].density == 4) &&
  99. (dram_width == X8) ? 11 : 10;
  100. /*
  101. * Determine row bits:
  102. *
  103. * 512Mbx16=12 512Mbx8=13
  104. * 1Gbx16=13 1Gbx8=14
  105. * 2Gbx16=14 2Gbx8=15
  106. * 4Gbx16=15 4Gbx8=16
  107. * 8Gbx16=16 8Gbx8=16
  108. */
  109. mrc_params->row_bits[0] = 12 + dram_params[0].density +
  110. (dram_params[0].density < 4) &&
  111. (dram_width == X8) ? 1 : 0;
  112. /*
  113. * Determine per-channel memory size:
  114. *
  115. * (For 2 RANKs, multiply by 2)
  116. * (For 16 bit data bus, divide by 2)
  117. *
  118. * DENSITY WIDTH MEM_AVAILABLE
  119. * 512Mb x16 0x008000000 ( 128MB)
  120. * 512Mb x8 0x010000000 ( 256MB)
  121. * 1Gb x16 0x010000000 ( 256MB)
  122. * 1Gb x8 0x020000000 ( 512MB)
  123. * 2Gb x16 0x020000000 ( 512MB)
  124. * 2Gb x8 0x040000000 (1024MB)
  125. * 4Gb x16 0x040000000 (1024MB)
  126. * 4Gb x8 0x080000000 (2048MB)
  127. */
  128. mrc_params->channel_size[0] = 1 << dram_params[0].density;
  129. mrc_params->channel_size[0] *= (dram_width == X8) ? 2 : 1;
  130. mrc_params->channel_size[0] *= (rank_enables == 0x3) ? 2 : 1;
  131. mrc_params->channel_size[0] *= (channel_width == X16) ? 1 : 2;
  132. /* Determine memory size (convert number of 64MB/512Mb units) */
  133. mrc_params->mem_size += mrc_params->channel_size[0] << 26;
  134. LEAVEFN();
  135. }
  136. static void mrc_mem_init(struct mrc_params *mrc_params)
  137. {
  138. int i;
  139. ENTERFN();
  140. /* MRC started */
  141. mrc_post_code(0x01, 0x00);
  142. if (mrc_params->boot_mode != BM_COLD) {
  143. if (mrc_params->ddr_speed != mrc_params->timings.ddr_speed) {
  144. /* full training required as frequency changed */
  145. mrc_params->boot_mode = BM_COLD;
  146. }
  147. }
  148. for (i = 0; i < ARRAY_SIZE(init); i++) {
  149. uint64_t my_tsc;
  150. if (mrc_params->boot_mode & init[i].boot_path) {
  151. uint8_t major = init[i].post_code >> 8 & 0xff;
  152. uint8_t minor = init[i].post_code >> 0 & 0xff;
  153. mrc_post_code(major, minor);
  154. my_tsc = rdtsc();
  155. init[i].init_fn(mrc_params);
  156. DPF(D_TIME, "Execution time %llx", rdtsc() - my_tsc);
  157. }
  158. }
  159. /* display the timings */
  160. print_timings(mrc_params);
  161. /* MRC complete */
  162. mrc_post_code(0x01, 0xff);
  163. LEAVEFN();
  164. }
  165. void mrc_init(struct mrc_params *mrc_params)
  166. {
  167. ENTERFN();
  168. DPF(D_INFO, "MRC Version %04x %s %s\n", MRC_VERSION,
  169. U_BOOT_DATE, U_BOOT_TIME);
  170. /* Set up the data structures used by mrc_mem_init() */
  171. mrc_adjust_params(mrc_params);
  172. /* Initialize system memory */
  173. mrc_mem_init(mrc_params);
  174. LEAVEFN();
  175. }