cpu.c 5.7 KB

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  1. /*
  2. * (C) Copyright 2008-2011
  3. * Graeme Russ, <graeme.russ@gmail.com>
  4. *
  5. * (C) Copyright 2002
  6. * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
  7. *
  8. * (C) Copyright 2002
  9. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  10. * Marius Groeger <mgroeger@sysgo.de>
  11. *
  12. * (C) Copyright 2002
  13. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  14. * Alex Zuepke <azu@sysgo.de>
  15. *
  16. * Part of this file is adapted from coreboot
  17. * src/arch/x86/lib/cpu.c
  18. *
  19. * SPDX-License-Identifier: GPL-2.0+
  20. */
  21. #include <common.h>
  22. #include <command.h>
  23. #include <dm.h>
  24. #include <errno.h>
  25. #include <malloc.h>
  26. #include <syscon.h>
  27. #include <asm/acpi_s3.h>
  28. #include <asm/acpi_table.h>
  29. #include <asm/control_regs.h>
  30. #include <asm/coreboot_tables.h>
  31. #include <asm/cpu.h>
  32. #include <asm/lapic.h>
  33. #include <asm/microcode.h>
  34. #include <asm/mp.h>
  35. #include <asm/mrccache.h>
  36. #include <asm/msr.h>
  37. #include <asm/mtrr.h>
  38. #include <asm/post.h>
  39. #include <asm/processor.h>
  40. #include <asm/processor-flags.h>
  41. #include <asm/interrupt.h>
  42. #include <asm/tables.h>
  43. #include <linux/compiler.h>
  44. DECLARE_GLOBAL_DATA_PTR;
  45. static const char *const x86_vendor_name[] = {
  46. [X86_VENDOR_INTEL] = "Intel",
  47. [X86_VENDOR_CYRIX] = "Cyrix",
  48. [X86_VENDOR_AMD] = "AMD",
  49. [X86_VENDOR_UMC] = "UMC",
  50. [X86_VENDOR_NEXGEN] = "NexGen",
  51. [X86_VENDOR_CENTAUR] = "Centaur",
  52. [X86_VENDOR_RISE] = "Rise",
  53. [X86_VENDOR_TRANSMETA] = "Transmeta",
  54. [X86_VENDOR_NSC] = "NSC",
  55. [X86_VENDOR_SIS] = "SiS",
  56. };
  57. int __weak x86_cleanup_before_linux(void)
  58. {
  59. #ifdef CONFIG_BOOTSTAGE_STASH
  60. bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
  61. CONFIG_BOOTSTAGE_STASH_SIZE);
  62. #endif
  63. return 0;
  64. }
  65. int x86_init_cache(void)
  66. {
  67. enable_caches();
  68. return 0;
  69. }
  70. int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
  71. int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  72. {
  73. printf("resetting ...\n");
  74. /* wait 50 ms */
  75. udelay(50000);
  76. disable_interrupts();
  77. reset_cpu(0);
  78. /*NOTREACHED*/
  79. return 0;
  80. }
  81. void flush_cache(unsigned long dummy1, unsigned long dummy2)
  82. {
  83. asm("wbinvd\n");
  84. }
  85. __weak void reset_cpu(ulong addr)
  86. {
  87. /* Do a hard reset through the chipset's reset control register */
  88. outb(SYS_RST | RST_CPU, IO_PORT_RESET);
  89. for (;;)
  90. cpu_hlt();
  91. }
  92. void x86_full_reset(void)
  93. {
  94. outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
  95. }
  96. /* Define these functions to allow ehch-hcd to function */
  97. void flush_dcache_range(unsigned long start, unsigned long stop)
  98. {
  99. }
  100. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  101. {
  102. }
  103. void dcache_enable(void)
  104. {
  105. enable_caches();
  106. }
  107. void dcache_disable(void)
  108. {
  109. disable_caches();
  110. }
  111. void icache_enable(void)
  112. {
  113. }
  114. void icache_disable(void)
  115. {
  116. }
  117. int icache_status(void)
  118. {
  119. return 1;
  120. }
  121. const char *cpu_vendor_name(int vendor)
  122. {
  123. const char *name;
  124. name = "<invalid cpu vendor>";
  125. if (vendor < ARRAY_SIZE(x86_vendor_name) &&
  126. x86_vendor_name[vendor])
  127. name = x86_vendor_name[vendor];
  128. return name;
  129. }
  130. char *cpu_get_name(char *name)
  131. {
  132. unsigned int *name_as_ints = (unsigned int *)name;
  133. struct cpuid_result regs;
  134. char *ptr;
  135. int i;
  136. /* This bit adds up to 48 bytes */
  137. for (i = 0; i < 3; i++) {
  138. regs = cpuid(0x80000002 + i);
  139. name_as_ints[i * 4 + 0] = regs.eax;
  140. name_as_ints[i * 4 + 1] = regs.ebx;
  141. name_as_ints[i * 4 + 2] = regs.ecx;
  142. name_as_ints[i * 4 + 3] = regs.edx;
  143. }
  144. name[CPU_MAX_NAME_LEN - 1] = '\0';
  145. /* Skip leading spaces. */
  146. ptr = name;
  147. while (*ptr == ' ')
  148. ptr++;
  149. return ptr;
  150. }
  151. int default_print_cpuinfo(void)
  152. {
  153. printf("CPU: %s, vendor %s, device %xh\n",
  154. cpu_has_64bit() ? "x86_64" : "x86",
  155. cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
  156. #ifdef CONFIG_HAVE_ACPI_RESUME
  157. debug("ACPI previous sleep state: %s\n",
  158. acpi_ss_string(gd->arch.prev_sleep_state));
  159. #endif
  160. return 0;
  161. }
  162. void show_boot_progress(int val)
  163. {
  164. outb(val, POST_PORT);
  165. }
  166. #ifndef CONFIG_SYS_COREBOOT
  167. /*
  168. * Implement a weak default function for boards that optionally
  169. * need to clean up the system before jumping to the kernel.
  170. */
  171. __weak void board_final_cleanup(void)
  172. {
  173. }
  174. int last_stage_init(void)
  175. {
  176. board_final_cleanup();
  177. #if CONFIG_HAVE_ACPI_RESUME
  178. struct acpi_fadt *fadt = acpi_find_fadt();
  179. if (fadt != NULL && gd->arch.prev_sleep_state == ACPI_S3)
  180. acpi_resume(fadt);
  181. #endif
  182. write_tables();
  183. return 0;
  184. }
  185. #endif
  186. static int x86_init_cpus(void)
  187. {
  188. #ifdef CONFIG_SMP
  189. debug("Init additional CPUs\n");
  190. x86_mp_init();
  191. #else
  192. struct udevice *dev;
  193. /*
  194. * This causes the cpu-x86 driver to be probed.
  195. * We don't check return value here as we want to allow boards
  196. * which have not been converted to use cpu uclass driver to boot.
  197. */
  198. uclass_first_device(UCLASS_CPU, &dev);
  199. #endif
  200. return 0;
  201. }
  202. int cpu_init_r(void)
  203. {
  204. struct udevice *dev;
  205. int ret;
  206. if (!ll_boot_init())
  207. return 0;
  208. ret = x86_init_cpus();
  209. if (ret)
  210. return ret;
  211. /*
  212. * Set up the northbridge, PCH and LPC if available. Note that these
  213. * may have had some limited pre-relocation init if they were probed
  214. * before relocation, but this is post relocation.
  215. */
  216. uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
  217. uclass_first_device(UCLASS_PCH, &dev);
  218. uclass_first_device(UCLASS_LPC, &dev);
  219. /* Set up pin control if available */
  220. ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
  221. debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
  222. return 0;
  223. }
  224. #ifndef CONFIG_EFI_STUB
  225. int reserve_arch(void)
  226. {
  227. #ifdef CONFIG_ENABLE_MRC_CACHE
  228. mrccache_reserve();
  229. #endif
  230. #ifdef CONFIG_SEABIOS
  231. high_table_reserve();
  232. #endif
  233. #ifdef CONFIG_HAVE_ACPI_RESUME
  234. acpi_s3_reserve();
  235. #ifdef CONFIG_HAVE_FSP
  236. /*
  237. * Save stack address to CMOS so that at next S3 boot,
  238. * we can use it as the stack address for fsp_contiue()
  239. */
  240. fsp_save_s3_stack();
  241. #endif /* CONFIG_HAVE_FSP */
  242. #endif /* CONFIG_HAVE_ACPI_RESUME */
  243. return 0;
  244. }
  245. #endif