coreboot.c 1.6 KB

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  1. /*
  2. * Copyright (c) 2011 The Chromium OS Authors.
  3. * (C) Copyright 2008
  4. * Graeme Russ, graeme.russ@gmail.com.
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <fdtdec.h>
  10. #include <asm/io.h>
  11. #include <asm/msr.h>
  12. #include <asm/mtrr.h>
  13. #include <asm/arch/sysinfo.h>
  14. #include <asm/arch/timestamp.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. int arch_cpu_init(void)
  17. {
  18. int ret = get_coreboot_info(&lib_sysinfo);
  19. if (ret != 0) {
  20. printf("Failed to parse coreboot tables.\n");
  21. return ret;
  22. }
  23. timestamp_init();
  24. return x86_cpu_init_f();
  25. }
  26. int checkcpu(void)
  27. {
  28. return 0;
  29. }
  30. int print_cpuinfo(void)
  31. {
  32. return default_print_cpuinfo();
  33. }
  34. static void board_final_cleanup(void)
  35. {
  36. /*
  37. * Un-cache the ROM so the kernel has one
  38. * more MTRR available.
  39. *
  40. * Coreboot should have assigned this to the
  41. * top available variable MTRR.
  42. */
  43. u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
  44. u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
  45. /* Make sure this MTRR is the correct Write-Protected type */
  46. if (top_type == MTRR_TYPE_WRPROT) {
  47. struct mtrr_state state;
  48. mtrr_open(&state);
  49. wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
  50. wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
  51. mtrr_close(&state);
  52. }
  53. if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) {
  54. /*
  55. * Issue SMI to coreboot to lock down ME and registers
  56. * when allowed via device tree
  57. */
  58. printf("Finalizing coreboot\n");
  59. outb(0xcb, 0xb2);
  60. }
  61. }
  62. int last_stage_init(void)
  63. {
  64. if (gd->flags & GD_FLG_COLD_BOOT)
  65. timestamp_add_to_bootstage();
  66. board_final_cleanup();
  67. return 0;
  68. }
  69. int misc_init_r(void)
  70. {
  71. return 0;
  72. }