clk-uclass.c 8.0 KB

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  1. /*
  2. * Copyright (C) 2015 Google, Inc
  3. * Written by Simon Glass <sjg@chromium.org>
  4. * Copyright (c) 2016, NVIDIA CORPORATION.
  5. * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <clk-uclass.h>
  12. #include <dm.h>
  13. #include <dm/read.h>
  14. #include <dt-structs.h>
  15. #include <errno.h>
  16. static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
  17. {
  18. return (const struct clk_ops *)dev->driver->ops;
  19. }
  20. #if CONFIG_IS_ENABLED(OF_CONTROL)
  21. # if CONFIG_IS_ENABLED(OF_PLATDATA)
  22. int clk_get_by_index_platdata(struct udevice *dev, int index,
  23. struct phandle_1_arg *cells, struct clk *clk)
  24. {
  25. int ret;
  26. if (index != 0)
  27. return -ENOSYS;
  28. ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
  29. if (ret)
  30. return ret;
  31. clk->id = cells[0].arg[0];
  32. return 0;
  33. }
  34. # else
  35. static int clk_of_xlate_default(struct clk *clk,
  36. struct ofnode_phandle_args *args)
  37. {
  38. debug("%s(clk=%p)\n", __func__, clk);
  39. if (args->args_count > 1) {
  40. debug("Invaild args_count: %d\n", args->args_count);
  41. return -EINVAL;
  42. }
  43. if (args->args_count)
  44. clk->id = args->args[0];
  45. else
  46. clk->id = 0;
  47. return 0;
  48. }
  49. static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
  50. int index, struct clk *clk)
  51. {
  52. int ret;
  53. struct ofnode_phandle_args args;
  54. struct udevice *dev_clk;
  55. const struct clk_ops *ops;
  56. debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
  57. assert(clk);
  58. clk->dev = NULL;
  59. ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
  60. index, &args);
  61. if (ret) {
  62. debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
  63. __func__, ret);
  64. return ret;
  65. }
  66. ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
  67. if (ret) {
  68. debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
  69. __func__, ret);
  70. return ret;
  71. }
  72. clk->dev = dev_clk;
  73. ops = clk_dev_ops(dev_clk);
  74. if (ops->of_xlate)
  75. ret = ops->of_xlate(clk, &args);
  76. else
  77. ret = clk_of_xlate_default(clk, &args);
  78. if (ret) {
  79. debug("of_xlate() failed: %d\n", ret);
  80. return ret;
  81. }
  82. return clk_request(dev_clk, clk);
  83. }
  84. int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
  85. {
  86. return clk_get_by_indexed_prop(dev, "clocks", index, clk);
  87. }
  88. int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
  89. {
  90. int i, ret, err, count;
  91. bulk->count = 0;
  92. count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
  93. if (!count)
  94. return 0;
  95. bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
  96. if (!bulk->clks)
  97. return -ENOMEM;
  98. for (i = 0; i < count; i++) {
  99. ret = clk_get_by_index(dev, i, &bulk->clks[i]);
  100. if (ret < 0)
  101. goto bulk_get_err;
  102. ++bulk->count;
  103. }
  104. return 0;
  105. bulk_get_err:
  106. err = clk_release_all(bulk->clks, bulk->count);
  107. if (err)
  108. debug("%s: could release all clocks for %p\n",
  109. __func__, dev);
  110. return ret;
  111. }
  112. static int clk_set_default_parents(struct udevice *dev)
  113. {
  114. struct clk clk, parent_clk;
  115. int index;
  116. int num_parents;
  117. int ret;
  118. num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
  119. "#clock-cells");
  120. if (num_parents < 0) {
  121. debug("%s: could not read assigned-clock-parents for %p\n",
  122. __func__, dev);
  123. return 0;
  124. }
  125. for (index = 0; index < num_parents; index++) {
  126. ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
  127. index, &parent_clk);
  128. if (ret) {
  129. debug("%s: could not get parent clock %d for %s\n",
  130. __func__, index, dev_read_name(dev));
  131. return ret;
  132. }
  133. ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  134. index, &clk);
  135. if (ret) {
  136. debug("%s: could not get assigned clock %d for %s\n",
  137. __func__, index, dev_read_name(dev));
  138. return ret;
  139. }
  140. ret = clk_set_parent(&clk, &parent_clk);
  141. /*
  142. * Not all drivers may support clock-reparenting (as of now).
  143. * Ignore errors due to this.
  144. */
  145. if (ret == -ENOSYS)
  146. continue;
  147. if (ret) {
  148. debug("%s: failed to reparent clock %d for %s\n",
  149. __func__, index, dev_read_name(dev));
  150. return ret;
  151. }
  152. }
  153. return 0;
  154. }
  155. static int clk_set_default_rates(struct udevice *dev)
  156. {
  157. struct clk clk;
  158. int index;
  159. int num_rates;
  160. int size;
  161. int ret = 0;
  162. u32 *rates = NULL;
  163. size = dev_read_size(dev, "assigned-clock-rates");
  164. if (size < 0)
  165. return 0;
  166. num_rates = size / sizeof(u32);
  167. rates = calloc(num_rates, sizeof(u32));
  168. if (!rates)
  169. return -ENOMEM;
  170. ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
  171. if (ret)
  172. goto fail;
  173. for (index = 0; index < num_rates; index++) {
  174. ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  175. index, &clk);
  176. if (ret) {
  177. debug("%s: could not get assigned clock %d for %s\n",
  178. __func__, index, dev_read_name(dev));
  179. continue;
  180. }
  181. ret = clk_set_rate(&clk, rates[index]);
  182. if (ret < 0) {
  183. debug("%s: failed to set rate on clock %d for %s\n",
  184. __func__, index, dev_read_name(dev));
  185. break;
  186. }
  187. }
  188. fail:
  189. free(rates);
  190. return ret;
  191. }
  192. int clk_set_defaults(struct udevice *dev)
  193. {
  194. int ret;
  195. /* If this is running pre-reloc state, don't take any action. */
  196. if (!(gd->flags & GD_FLG_RELOC))
  197. return 0;
  198. debug("%s(%s)\n", __func__, dev_read_name(dev));
  199. ret = clk_set_default_parents(dev);
  200. if (ret)
  201. return ret;
  202. ret = clk_set_default_rates(dev);
  203. if (ret < 0)
  204. return ret;
  205. return 0;
  206. }
  207. # endif /* OF_PLATDATA */
  208. int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
  209. {
  210. int index;
  211. debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
  212. clk->dev = NULL;
  213. index = dev_read_stringlist_search(dev, "clock-names", name);
  214. if (index < 0) {
  215. debug("fdt_stringlist_search() failed: %d\n", index);
  216. return index;
  217. }
  218. return clk_get_by_index(dev, index, clk);
  219. }
  220. int clk_release_all(struct clk *clk, int count)
  221. {
  222. int i, ret;
  223. for (i = 0; i < count; i++) {
  224. debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
  225. /* check if clock has been previously requested */
  226. if (!clk[i].dev)
  227. continue;
  228. ret = clk_disable(&clk[i]);
  229. if (ret && ret != -ENOSYS)
  230. return ret;
  231. ret = clk_free(&clk[i]);
  232. if (ret && ret != -ENOSYS)
  233. return ret;
  234. }
  235. return 0;
  236. }
  237. #endif /* OF_CONTROL */
  238. int clk_request(struct udevice *dev, struct clk *clk)
  239. {
  240. const struct clk_ops *ops = clk_dev_ops(dev);
  241. debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
  242. clk->dev = dev;
  243. if (!ops->request)
  244. return 0;
  245. return ops->request(clk);
  246. }
  247. int clk_free(struct clk *clk)
  248. {
  249. const struct clk_ops *ops = clk_dev_ops(clk->dev);
  250. debug("%s(clk=%p)\n", __func__, clk);
  251. if (!ops->free)
  252. return 0;
  253. return ops->free(clk);
  254. }
  255. ulong clk_get_rate(struct clk *clk)
  256. {
  257. const struct clk_ops *ops = clk_dev_ops(clk->dev);
  258. debug("%s(clk=%p)\n", __func__, clk);
  259. if (!ops->get_rate)
  260. return -ENOSYS;
  261. return ops->get_rate(clk);
  262. }
  263. ulong clk_set_rate(struct clk *clk, ulong rate)
  264. {
  265. const struct clk_ops *ops = clk_dev_ops(clk->dev);
  266. debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
  267. if (!ops->set_rate)
  268. return -ENOSYS;
  269. return ops->set_rate(clk, rate);
  270. }
  271. int clk_set_parent(struct clk *clk, struct clk *parent)
  272. {
  273. const struct clk_ops *ops = clk_dev_ops(clk->dev);
  274. debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
  275. if (!ops->set_parent)
  276. return -ENOSYS;
  277. return ops->set_parent(clk, parent);
  278. }
  279. int clk_enable(struct clk *clk)
  280. {
  281. const struct clk_ops *ops = clk_dev_ops(clk->dev);
  282. debug("%s(clk=%p)\n", __func__, clk);
  283. if (!ops->enable)
  284. return -ENOSYS;
  285. return ops->enable(clk);
  286. }
  287. int clk_enable_bulk(struct clk_bulk *bulk)
  288. {
  289. int i, ret;
  290. for (i = 0; i < bulk->count; i++) {
  291. ret = clk_enable(&bulk->clks[i]);
  292. if (ret < 0 && ret != -ENOSYS)
  293. return ret;
  294. }
  295. return 0;
  296. }
  297. int clk_disable(struct clk *clk)
  298. {
  299. const struct clk_ops *ops = clk_dev_ops(clk->dev);
  300. debug("%s(clk=%p)\n", __func__, clk);
  301. if (!ops->disable)
  302. return -ENOSYS;
  303. return ops->disable(clk);
  304. }
  305. int clk_disable_bulk(struct clk_bulk *bulk)
  306. {
  307. int i, ret;
  308. for (i = 0; i < bulk->count; i++) {
  309. ret = clk_disable(&bulk->clks[i]);
  310. if (ret < 0 && ret != -ENOSYS)
  311. return ret;
  312. }
  313. return 0;
  314. }
  315. UCLASS_DRIVER(clk) = {
  316. .id = UCLASS_CLK,
  317. .name = "clk",
  318. };