zynq_sdhci.c 2.5 KB

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  1. /*
  2. * (C) Copyright 2013 - 2015 Xilinx, Inc.
  3. *
  4. * Xilinx Zynq SD Host Controller Interface
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <clk.h>
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <fdtdec.h>
  12. #include <libfdt.h>
  13. #include <malloc.h>
  14. #include <sdhci.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
  17. # define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
  18. #endif
  19. struct arasan_sdhci_plat {
  20. struct mmc_config cfg;
  21. struct mmc mmc;
  22. unsigned int f_max;
  23. };
  24. static int arasan_sdhci_probe(struct udevice *dev)
  25. {
  26. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  27. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  28. struct sdhci_host *host = dev_get_priv(dev);
  29. struct clk clk;
  30. unsigned long clock;
  31. int ret;
  32. ret = clk_get_by_index(dev, 0, &clk);
  33. if (ret < 0) {
  34. dev_err(dev, "failed to get clock\n");
  35. return ret;
  36. }
  37. clock = clk_get_rate(&clk);
  38. if (IS_ERR_VALUE(clock)) {
  39. dev_err(dev, "failed to get rate\n");
  40. return clock;
  41. }
  42. debug("%s: CLK %ld\n", __func__, clock);
  43. ret = clk_enable(&clk);
  44. if (ret && ret != -ENOSYS) {
  45. dev_err(dev, "failed to enable clock\n");
  46. return ret;
  47. }
  48. host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
  49. SDHCI_QUIRK_BROKEN_R1B;
  50. #ifdef CONFIG_ZYNQ_HISPD_BROKEN
  51. host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
  52. #endif
  53. host->max_clk = clock;
  54. ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
  55. CONFIG_ZYNQ_SDHCI_MIN_FREQ);
  56. host->mmc = &plat->mmc;
  57. if (ret)
  58. return ret;
  59. host->mmc->priv = host;
  60. host->mmc->dev = dev;
  61. upriv->mmc = host->mmc;
  62. return sdhci_probe(dev);
  63. }
  64. static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
  65. {
  66. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  67. struct sdhci_host *host = dev_get_priv(dev);
  68. host->name = dev->name;
  69. host->ioaddr = (void *)devfdt_get_addr(dev);
  70. plat->f_max = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
  71. "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
  72. return 0;
  73. }
  74. static int arasan_sdhci_bind(struct udevice *dev)
  75. {
  76. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  77. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  78. }
  79. static const struct udevice_id arasan_sdhci_ids[] = {
  80. { .compatible = "arasan,sdhci-8.9a" },
  81. { }
  82. };
  83. U_BOOT_DRIVER(arasan_sdhci_drv) = {
  84. .name = "arasan_sdhci",
  85. .id = UCLASS_MMC,
  86. .of_match = arasan_sdhci_ids,
  87. .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
  88. .ops = &sdhci_ops,
  89. .bind = arasan_sdhci_bind,
  90. .probe = arasan_sdhci_probe,
  91. .priv_auto_alloc_size = sizeof(struct sdhci_host),
  92. .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
  93. };