ddr3.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427
  1. /*
  2. * Keystone2: DDR3 initialization
  3. *
  4. * (C) Copyright 2012-2014
  5. * Texas Instruments Incorporated, <www.ti.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <asm/io.h>
  10. #include <common.h>
  11. #include <asm/arch/msmc.h>
  12. #include <asm/arch/ddr3.h>
  13. #include <asm/arch/psc_defs.h>
  14. #include <asm/ti-common/ti-edma3.h>
  15. #define DDR3_EDMA_BLK_SIZE_SHIFT 10
  16. #define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT)
  17. #define DDR3_EDMA_BCNT 0x8000
  18. #define DDR3_EDMA_CCNT 1
  19. #define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
  20. #define DDR3_EDMA_SLOT_NUM 1
  21. void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
  22. {
  23. unsigned int tmp;
  24. while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
  25. & 0x00000001) != 0x00000001)
  26. ;
  27. __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
  28. tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
  29. tmp &= ~(phy_cfg->pgcr1_mask);
  30. tmp |= phy_cfg->pgcr1_val;
  31. __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
  32. __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET);
  33. __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET);
  34. __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET);
  35. __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET);
  36. tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
  37. tmp &= ~(phy_cfg->dcr_mask);
  38. tmp |= phy_cfg->dcr_val;
  39. __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
  40. __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
  41. __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
  42. __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
  43. __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
  44. __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
  45. __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
  46. __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
  47. __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
  48. __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
  49. __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
  50. __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
  51. __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
  52. while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
  53. ;
  54. if (cpu_is_k2g()) {
  55. setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
  56. clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
  57. clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
  58. clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
  59. clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
  60. }
  61. __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
  62. while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
  63. ;
  64. }
  65. void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
  66. {
  67. __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
  68. __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
  69. __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
  70. __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
  71. __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
  72. __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
  73. __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
  74. }
  75. int ddr3_ecc_support_rmw(u32 base)
  76. {
  77. u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);
  78. /* Check the DDR3 controller ID reg if the controllers
  79. supports ECC RMW or not */
  80. if (value == 0x40461C02)
  81. return 1;
  82. return 0;
  83. }
  84. static void ddr3_ecc_config(u32 base, u32 value)
  85. {
  86. u32 data;
  87. __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET);
  88. udelay(100000); /* delay required to synchronize across clock domains */
  89. if (value & KS2_DDR3_ECC_EN) {
  90. /* Clear the 1-bit error count */
  91. data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
  92. __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
  93. /* enable the ECC interrupt */
  94. __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
  95. KS2_DDR3_WR_ECC_ERR_SYS,
  96. base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);
  97. /* Clear the ECC error interrupt status */
  98. __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
  99. KS2_DDR3_WR_ECC_ERR_SYS,
  100. base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
  101. }
  102. }
  103. static void ddr3_reset_data(u32 base, u32 ddr3_size)
  104. {
  105. u32 mpax[2];
  106. u32 seg_num;
  107. u32 seg, blks, dst, edma_blks;
  108. struct edma3_slot_config slot;
  109. struct edma3_channel_config edma_channel;
  110. u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
  111. /* Setup an edma to copy the 1k block to the entire DDR */
  112. puts("\nClear entire DDR3 memory to enable ECC\n");
  113. /* save the SES MPAX regs */
  114. if (cpu_is_k2g())
  115. msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
  116. else
  117. msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
  118. /* setup edma slot 1 configuration */
  119. slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
  120. EDMA3_SLOPT_COMP_CODE(0) |
  121. EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
  122. slot.bcnt = DDR3_EDMA_BCNT;
  123. slot.acnt = DDR3_EDMA_BLK_SIZE;
  124. slot.ccnt = DDR3_EDMA_CCNT;
  125. slot.src_bidx = 0;
  126. slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
  127. slot.src_cidx = 0;
  128. slot.dst_cidx = 0;
  129. slot.link = EDMA3_PARSET_NULL_LINK;
  130. slot.bcntrld = 0;
  131. edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot);
  132. /* configure quik edma channel */
  133. edma_channel.slot = DDR3_EDMA_SLOT_NUM;
  134. edma_channel.chnum = 0;
  135. edma_channel.complete_code = 0;
  136. /* event trigger after dst update */
  137. edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
  138. qedma3_start(KS2_EDMA0_BASE, &edma_channel);
  139. /* DDR3 size in segments (4KB seg size) */
  140. seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);
  141. for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
  142. /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
  143. access slave interface so that edma driver can access */
  144. if (cpu_is_k2g()) {
  145. msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0,
  146. base >> KS2_MSMC_SEG_SIZE_SHIFT,
  147. KS2_MSMC_DST_SEG_BASE + seg,
  148. MPAX_SEG_2G);
  149. } else {
  150. msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0,
  151. base >> KS2_MSMC_SEG_SIZE_SHIFT,
  152. KS2_MSMC_DST_SEG_BASE + seg,
  153. MPAX_SEG_2G);
  154. }
  155. if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
  156. edma_blks = KS2_MSMC_MAP_SEG_NUM <<
  157. (KS2_MSMC_SEG_SIZE_SHIFT
  158. - DDR3_EDMA_BLK_SIZE_SHIFT);
  159. else
  160. edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
  161. - DDR3_EDMA_BLK_SIZE_SHIFT);
  162. /* Use edma driver to scrub 2GB DDR memory */
  163. for (dst = base, blks = 0; blks < edma_blks;
  164. blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
  165. edma3_set_src_addr(KS2_EDMA0_BASE,
  166. edma_channel.slot, (u32)edma_src);
  167. edma3_set_dest_addr(KS2_EDMA0_BASE,
  168. edma_channel.slot, (u32)dst);
  169. while (edma3_check_for_transfer(KS2_EDMA0_BASE,
  170. &edma_channel))
  171. udelay(10);
  172. }
  173. }
  174. qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
  175. /* restore the SES MPAX regs */
  176. if (cpu_is_k2g())
  177. msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
  178. else
  179. msmc_set_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
  180. }
  181. static void ddr3_ecc_init_range(u32 base)
  182. {
  183. u32 ecc_val = KS2_DDR3_ECC_EN;
  184. u32 rmw = ddr3_ecc_support_rmw(base);
  185. if (rmw)
  186. ecc_val |= KS2_DDR3_ECC_RMW_EN;
  187. __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
  188. ddr3_ecc_config(base, ecc_val);
  189. }
  190. void ddr3_enable_ecc(u32 base, int test)
  191. {
  192. u32 ecc_val = KS2_DDR3_ECC_ENABLE;
  193. u32 rmw = ddr3_ecc_support_rmw(base);
  194. if (test)
  195. ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN;
  196. if (!rmw) {
  197. if (!test)
  198. /* by default, disable ecc when rmw = 0 and no
  199. ecc test */
  200. ecc_val = 0;
  201. } else {
  202. ecc_val |= KS2_DDR3_ECC_RMW_EN;
  203. }
  204. ddr3_ecc_config(base, ecc_val);
  205. }
  206. void ddr3_disable_ecc(u32 base)
  207. {
  208. ddr3_ecc_config(base, 0);
  209. }
  210. #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
  211. static void cic_init(u32 base)
  212. {
  213. /* Disable CIC global interrupts */
  214. __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);
  215. /* Set to normal mode, no nesting, no priority hold */
  216. __raw_writel(0, base + KS2_CIC_CTRL);
  217. __raw_writel(0, base + KS2_CIC_HOST_CTRL);
  218. /* Enable CIC global interrupts */
  219. __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);
  220. }
  221. static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num)
  222. {
  223. /* Map the system interrupt to a CIC channel */
  224. __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num);
  225. /* Enable CIC system interrupt */
  226. __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);
  227. /* Enable CIC Host interrupt */
  228. __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);
  229. }
  230. static void ddr3_map_ecc_cic2_irq(u32 base)
  231. {
  232. cic_init(base);
  233. cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM,
  234. KS2_CIC2_DDR3_ECC_IRQ_NUM);
  235. }
  236. #endif
  237. void ddr3_init_ecc(u32 base, u32 ddr3_size)
  238. {
  239. if (!ddr3_ecc_support_rmw(base)) {
  240. ddr3_disable_ecc(base);
  241. return;
  242. }
  243. ddr3_ecc_init_range(base);
  244. ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
  245. /* mapping DDR3 ECC system interrupt from CIC2 to GIC */
  246. #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
  247. ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE);
  248. #endif
  249. ddr3_enable_ecc(base, 0);
  250. }
  251. void ddr3_check_ecc_int(u32 base)
  252. {
  253. char *env;
  254. int ecc_test = 0;
  255. u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
  256. env = getenv("ecc_test");
  257. if (env)
  258. ecc_test = simple_strtol(env, NULL, 0);
  259. if (value & KS2_DDR3_WR_ECC_ERR_SYS)
  260. puts("DDR3 ECC write error interrupted\n");
  261. if (value & KS2_DDR3_2B_ECC_ERR_SYS) {
  262. puts("DDR3 ECC 2-bit error interrupted\n");
  263. if (!ecc_test) {
  264. puts("Reseting the device ...\n");
  265. reset_cpu(0);
  266. }
  267. }
  268. value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
  269. if (value) {
  270. printf("1-bit ECC err count: 0x%x\n", value);
  271. value = __raw_readl(base +
  272. KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET);
  273. printf("1-bit ECC err address log: 0x%x\n", value);
  274. }
  275. }
  276. void ddr3_reset_ddrphy(void)
  277. {
  278. u32 tmp;
  279. /* Assert DDR3A PHY reset */
  280. tmp = readl(KS2_DDR3APLLCTL1);
  281. tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
  282. writel(tmp, KS2_DDR3APLLCTL1);
  283. /* wait 10us to catch the reset */
  284. udelay(10);
  285. /* Release DDR3A PHY reset */
  286. tmp = readl(KS2_DDR3APLLCTL1);
  287. tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
  288. __raw_writel(tmp, KS2_DDR3APLLCTL1);
  289. }
  290. #ifdef CONFIG_SOC_K2HK
  291. /**
  292. * ddr3_reset_workaround - reset workaround in case if leveling error
  293. * detected for PG 1.0 and 1.1 k2hk SoCs
  294. */
  295. void ddr3_err_reset_workaround(void)
  296. {
  297. unsigned int tmp;
  298. unsigned int tmp_a;
  299. unsigned int tmp_b;
  300. /*
  301. * Check for PGSR0 error bits of DDR3 PHY.
  302. * Check for WLERR, QSGERR, WLAERR,
  303. * RDERR, WDERR, REERR, WEERR error to see if they are set or not
  304. */
  305. tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
  306. tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
  307. if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) {
  308. printf("DDR Leveling Error Detected!\n");
  309. printf("DDR3A PGSR0 = 0x%x\n", tmp_a);
  310. printf("DDR3B PGSR0 = 0x%x\n", tmp_b);
  311. /*
  312. * Write Keys to KICK registers to enable writes to registers
  313. * in boot config space
  314. */
  315. __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
  316. __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
  317. /*
  318. * Move DDR3A Module out of reset isolation by setting
  319. * MDCTL23[12] = 0
  320. */
  321. tmp_a = __raw_readl(KS2_PSC_BASE +
  322. PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
  323. tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
  324. __raw_writel(tmp_a, KS2_PSC_BASE +
  325. PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
  326. /*
  327. * Move DDR3B Module out of reset isolation by setting
  328. * MDCTL24[12] = 0
  329. */
  330. tmp_b = __raw_readl(KS2_PSC_BASE +
  331. PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
  332. tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
  333. __raw_writel(tmp_b, KS2_PSC_BASE +
  334. PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
  335. /*
  336. * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
  337. * to RSTCTRL and RSTCFG
  338. */
  339. tmp = __raw_readl(KS2_RSTCTRL);
  340. tmp &= KS2_RSTCTRL_MASK;
  341. tmp |= KS2_RSTCTRL_KEY;
  342. __raw_writel(tmp, KS2_RSTCTRL);
  343. /*
  344. * Set PLL Controller to drive hard reset on SW trigger by
  345. * setting RSTCFG[13] = 0
  346. */
  347. tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
  348. tmp &= ~KS2_RSTYPE_PLL_SOFT;
  349. __raw_writel(tmp, KS2_RSTCTRL_RSCFG);
  350. reset_cpu(0);
  351. }
  352. }
  353. #endif