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  1. /*
  2. * armboot - Startup Code for ARM926EJS CPU-core
  3. *
  4. * Copyright (c) 2003 Texas Instruments
  5. *
  6. * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
  7. *
  8. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  9. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  10. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  11. * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  12. * Copyright (c) 2003 Kshitij <kshitij@ti.com>
  13. *
  14. * See file CREDITS for list of people who contributed to this
  15. * project.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation; either version 2 of
  20. * the License, or (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30. * MA 02111-1307 USA
  31. */
  32. #include <config.h>
  33. #include <version.h>
  34. /*
  35. *************************************************************************
  36. *
  37. * Jump vector table
  38. *
  39. *************************************************************************
  40. */
  41. .globl _start
  42. _start:
  43. b reset
  44. ldr pc, _undefined_instruction
  45. ldr pc, _software_interrupt
  46. ldr pc, _prefetch_abort
  47. ldr pc, _data_abort
  48. ldr pc, _not_used
  49. ldr pc, _irq
  50. ldr pc, _fiq
  51. _undefined_instruction:
  52. .word undefined_instruction
  53. _software_interrupt:
  54. .word software_interrupt
  55. _prefetch_abort:
  56. .word prefetch_abort
  57. _data_abort:
  58. .word data_abort
  59. _not_used:
  60. .word not_used
  61. _irq:
  62. .word irq
  63. _fiq:
  64. .word fiq
  65. .balignl 16,0xdeadbeef
  66. /*
  67. *************************************************************************
  68. *
  69. * Startup Code (reset vector)
  70. *
  71. * do important init only if we don't start from memory!
  72. * setup memory and board specific bits prior to relocation.
  73. * relocate armboot to ram
  74. * setup stack
  75. *
  76. *************************************************************************
  77. */
  78. _TEXT_BASE:
  79. .word TEXT_BASE /* address of _start in the linked image */
  80. .globl _armboot_start
  81. _armboot_start:
  82. .word _start
  83. /*
  84. * These are defined in the board-specific linker script.
  85. */
  86. .globl _bss_start
  87. _bss_start:
  88. .word __bss_start
  89. .globl _bss_end
  90. _bss_end:
  91. .word _end
  92. #ifdef CONFIG_USE_IRQ
  93. /* IRQ stack memory (calculated at run-time) */
  94. .globl IRQ_STACK_START
  95. IRQ_STACK_START:
  96. .word 0x0badc0de
  97. /* IRQ stack memory (calculated at run-time) */
  98. .globl FIQ_STACK_START
  99. FIQ_STACK_START:
  100. .word 0x0badc0de
  101. #endif
  102. /*
  103. * the actual reset code
  104. */
  105. .globl reset
  106. reset:
  107. /*
  108. * set the cpu to SVC32 mode
  109. */
  110. mrs r0,cpsr
  111. bic r0,r0,#0x1f
  112. orr r0,r0,#0xd3
  113. msr cpsr,r0
  114. /*
  115. * we do sys-critical inits only at reboot,
  116. * not when booting from ram!
  117. */
  118. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  119. bl cpu_init_crit
  120. #endif
  121. relocate: /* relocate U-Boot to RAM */
  122. adr r0, _start /* pc relative address of label */
  123. ldr r1, _TEXT_BASE /* linked image address of label */
  124. cmp r0, r1 /* test if we run from flash or RAM */
  125. beq stack_setup /* ifeq we are in the RAM copy */
  126. ldr r2, _armboot_start
  127. ldr r3, _bss_start
  128. sub r2, r3, r2 /* r2 <- size of armboot */
  129. add r2, r0, r2 /* r2 <- source end address */
  130. copy_loop:
  131. ldmia r0!, {r3-r10} /* copy from source address [r0] */
  132. stmia r1!, {r3-r10} /* copy to target address [r1] */
  133. cmp r0, r2 /* until source end addreee [r2] */
  134. ble copy_loop
  135. /* Set up the stack */
  136. stack_setup:
  137. ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
  138. sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
  139. sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
  140. #ifdef CONFIG_USE_IRQ
  141. sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
  142. #endif
  143. sub sp, r0, #12 /* leave 3 words for abort-stack */
  144. bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
  145. clear_bss:
  146. ldr r0, _bss_start /* find start of bss segment */
  147. ldr r1, _bss_end /* stop here */
  148. mov r2, #0x00000000 /* clear */
  149. clbss_l:str r2, [r0] /* clear loop... */
  150. add r0, r0, #4
  151. cmp r0, r1
  152. ble clbss_l
  153. ldr pc, _start_armboot
  154. _start_armboot:
  155. .word start_armboot
  156. /*
  157. *************************************************************************
  158. *
  159. * CPU_init_critical registers
  160. *
  161. * setup important registers
  162. * setup memory timing
  163. *
  164. *************************************************************************
  165. */
  166. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  167. cpu_init_crit:
  168. /* arm_int_generic assumes the ARM boot monitor, or user software,
  169. * has initialized the platform
  170. */
  171. mov pc, lr /* back to my caller */
  172. #endif
  173. /*
  174. *************************************************************************
  175. *
  176. * Interrupt handling
  177. *
  178. *************************************************************************
  179. */
  180. @
  181. @ IRQ stack frame.
  182. @
  183. #define S_FRAME_SIZE 72
  184. #define S_OLD_R0 68
  185. #define S_PSR 64
  186. #define S_PC 60
  187. #define S_LR 56
  188. #define S_SP 52
  189. #define S_IP 48
  190. #define S_FP 44
  191. #define S_R10 40
  192. #define S_R9 36
  193. #define S_R8 32
  194. #define S_R7 28
  195. #define S_R6 24
  196. #define S_R5 20
  197. #define S_R4 16
  198. #define S_R3 12
  199. #define S_R2 8
  200. #define S_R1 4
  201. #define S_R0 0
  202. #define MODE_SVC 0x13
  203. #define I_BIT 0x80
  204. /*
  205. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  206. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  207. */
  208. .macro bad_save_user_regs
  209. @ carve out a frame on current user stack
  210. sub sp, sp, #S_FRAME_SIZE
  211. stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
  212. ldr r2, _armboot_start
  213. sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
  214. sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
  215. @ get values for "aborted" pc and cpsr (into parm regs)
  216. ldmia r2, {r2 - r3}
  217. add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
  218. add r5, sp, #S_SP
  219. mov r1, lr
  220. stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
  221. mov r0, sp @ save current stack into r0 (param register)
  222. .endm
  223. .macro irq_save_user_regs
  224. sub sp, sp, #S_FRAME_SIZE
  225. stmia sp, {r0 - r12} @ Calling r0-r12
  226. @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
  227. add r8, sp, #S_PC
  228. stmdb r8, {sp, lr}^ @ Calling SP, LR
  229. str lr, [r8, #0] @ Save calling PC
  230. mrs r6, spsr
  231. str r6, [r8, #4] @ Save CPSR
  232. str r0, [r8, #8] @ Save OLD_R0
  233. mov r0, sp
  234. .endm
  235. .macro irq_restore_user_regs
  236. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  237. mov r0, r0
  238. ldr lr, [sp, #S_PC] @ Get PC
  239. add sp, sp, #S_FRAME_SIZE
  240. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  241. .endm
  242. .macro get_bad_stack
  243. ldr r13, _armboot_start @ setup our mode stack
  244. sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
  245. sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
  246. str lr, [r13] @ save caller lr in position 0 of saved stack
  247. mrs lr, spsr @ get the spsr
  248. str lr, [r13, #4] @ save spsr in position 1 of saved stack
  249. mov r13, #MODE_SVC @ prepare SVC-Mode
  250. @ msr spsr_c, r13
  251. msr spsr, r13 @ switch modes, make sure moves will execute
  252. mov lr, pc @ capture return pc
  253. movs pc, lr @ jump to next instruction & switch modes.
  254. .endm
  255. .macro get_irq_stack @ setup IRQ stack
  256. ldr sp, IRQ_STACK_START
  257. .endm
  258. .macro get_fiq_stack @ setup FIQ stack
  259. ldr sp, FIQ_STACK_START
  260. .endm
  261. /*
  262. * exception handlers
  263. */
  264. .align 5
  265. .globl undefined_instruction
  266. undefined_instruction:
  267. get_bad_stack
  268. bad_save_user_regs
  269. bl do_undefined_instruction
  270. .align 5
  271. .globl software_interrupt
  272. software_interrupt:
  273. get_bad_stack
  274. bad_save_user_regs
  275. bl do_software_interrupt
  276. .align 5
  277. .globl prefetch_abort
  278. prefetch_abort:
  279. get_bad_stack
  280. bad_save_user_regs
  281. bl do_prefetch_abort
  282. .align 5
  283. .globl data_abort
  284. data_abort:
  285. get_bad_stack
  286. bad_save_user_regs
  287. bl do_data_abort
  288. .align 5
  289. .globl not_used
  290. not_used:
  291. get_bad_stack
  292. bad_save_user_regs
  293. bl do_not_used
  294. #ifdef CONFIG_USE_IRQ
  295. .align 5
  296. .globl irq
  297. irq:
  298. get_irq_stack
  299. irq_save_user_regs
  300. bl do_irq
  301. irq_restore_user_regs
  302. .align 5
  303. .globl fiq
  304. fiq:
  305. get_fiq_stack
  306. /* someone ought to write a more effiction fiq_save_user_regs */
  307. irq_save_user_regs
  308. bl do_fiq
  309. irq_restore_user_regs
  310. #else
  311. .align 5
  312. .globl irq
  313. irq:
  314. get_bad_stack
  315. bad_save_user_regs
  316. bl do_irq
  317. .align 5
  318. .globl fiq
  319. fiq:
  320. get_bad_stack
  321. bad_save_user_regs
  322. bl do_fiq
  323. #endif