sf_ops.c 16 KB

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  1. /*
  2. * SPI flash operations
  3. *
  4. * Copyright (C) 2008 Atmel Corporation
  5. * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
  6. * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <common.h>
  11. #include <errno.h>
  12. #include <malloc.h>
  13. #include <spi.h>
  14. #include <spi_flash.h>
  15. #include <watchdog.h>
  16. #include <linux/compiler.h>
  17. #include <linux/log2.h>
  18. #include "sf_internal.h"
  19. static void spi_flash_addr(u32 addr, u8 *cmd)
  20. {
  21. /* cmd[0] is actual command */
  22. cmd[1] = addr >> 16;
  23. cmd[2] = addr >> 8;
  24. cmd[3] = addr >> 0;
  25. }
  26. int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
  27. {
  28. int ret;
  29. u8 cmd;
  30. cmd = CMD_READ_STATUS;
  31. ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
  32. if (ret < 0) {
  33. debug("SF: fail to read status register\n");
  34. return ret;
  35. }
  36. return 0;
  37. }
  38. static int read_fsr(struct spi_flash *flash, u8 *fsr)
  39. {
  40. int ret;
  41. const u8 cmd = CMD_FLAG_STATUS;
  42. ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1);
  43. if (ret < 0) {
  44. debug("SF: fail to read flag status register\n");
  45. return ret;
  46. }
  47. return 0;
  48. }
  49. int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws)
  50. {
  51. u8 cmd;
  52. int ret;
  53. cmd = CMD_WRITE_STATUS;
  54. ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1);
  55. if (ret < 0) {
  56. debug("SF: fail to write status register\n");
  57. return ret;
  58. }
  59. return 0;
  60. }
  61. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  62. int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc)
  63. {
  64. int ret;
  65. u8 cmd;
  66. cmd = CMD_READ_CONFIG;
  67. ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
  68. if (ret < 0) {
  69. debug("SF: fail to read config register\n");
  70. return ret;
  71. }
  72. return 0;
  73. }
  74. int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
  75. {
  76. u8 data[2];
  77. u8 cmd;
  78. int ret;
  79. ret = spi_flash_cmd_read_status(flash, &data[0]);
  80. if (ret < 0)
  81. return ret;
  82. cmd = CMD_WRITE_STATUS;
  83. data[1] = wc;
  84. ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
  85. if (ret) {
  86. debug("SF: fail to write config register\n");
  87. return ret;
  88. }
  89. return 0;
  90. }
  91. #endif
  92. #ifdef CONFIG_SPI_FLASH_BAR
  93. static int spi_flash_write_bank(struct spi_flash *flash, u32 offset)
  94. {
  95. u8 cmd, bank_sel;
  96. int ret;
  97. bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
  98. if (bank_sel == flash->bank_curr)
  99. goto bar_end;
  100. cmd = flash->bank_write_cmd;
  101. ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
  102. if (ret < 0) {
  103. debug("SF: fail to write bank register\n");
  104. return ret;
  105. }
  106. bar_end:
  107. flash->bank_curr = bank_sel;
  108. return flash->bank_curr;
  109. }
  110. #endif
  111. #ifdef CONFIG_SF_DUAL_FLASH
  112. static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr)
  113. {
  114. switch (flash->dual_flash) {
  115. case SF_DUAL_STACKED_FLASH:
  116. if (*addr >= (flash->size >> 1)) {
  117. *addr -= flash->size >> 1;
  118. flash->spi->flags |= SPI_XFER_U_PAGE;
  119. } else {
  120. flash->spi->flags &= ~SPI_XFER_U_PAGE;
  121. }
  122. break;
  123. case SF_DUAL_PARALLEL_FLASH:
  124. *addr >>= flash->shift;
  125. break;
  126. default:
  127. debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash);
  128. break;
  129. }
  130. }
  131. #endif
  132. static int spi_flash_sr_ready(struct spi_flash *flash)
  133. {
  134. u8 sr;
  135. int ret;
  136. ret = spi_flash_cmd_read_status(flash, &sr);
  137. if (ret < 0)
  138. return ret;
  139. return !(sr & STATUS_WIP);
  140. }
  141. static int spi_flash_fsr_ready(struct spi_flash *flash)
  142. {
  143. u8 fsr;
  144. int ret;
  145. ret = read_fsr(flash, &fsr);
  146. if (ret < 0)
  147. return ret;
  148. return fsr & STATUS_PEC;
  149. }
  150. static int spi_flash_ready(struct spi_flash *flash)
  151. {
  152. int sr, fsr;
  153. sr = spi_flash_sr_ready(flash);
  154. if (sr < 0)
  155. return sr;
  156. fsr = 1;
  157. if (flash->flags & SNOR_F_USE_FSR) {
  158. fsr = spi_flash_fsr_ready(flash);
  159. if (fsr < 0)
  160. return fsr;
  161. }
  162. return sr && fsr;
  163. }
  164. int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
  165. {
  166. int timebase, ret;
  167. timebase = get_timer(0);
  168. while (get_timer(timebase) < timeout) {
  169. ret = spi_flash_ready(flash);
  170. if (ret < 0)
  171. return ret;
  172. if (ret)
  173. return 0;
  174. }
  175. printf("SF: Timeout!\n");
  176. return -ETIMEDOUT;
  177. }
  178. int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
  179. size_t cmd_len, const void *buf, size_t buf_len)
  180. {
  181. struct spi_slave *spi = flash->spi;
  182. unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
  183. int ret;
  184. if (buf == NULL)
  185. timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
  186. ret = spi_claim_bus(flash->spi);
  187. if (ret) {
  188. debug("SF: unable to claim SPI bus\n");
  189. return ret;
  190. }
  191. ret = spi_flash_cmd_write_enable(flash);
  192. if (ret < 0) {
  193. debug("SF: enabling write failed\n");
  194. return ret;
  195. }
  196. ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
  197. if (ret < 0) {
  198. debug("SF: write cmd failed\n");
  199. return ret;
  200. }
  201. ret = spi_flash_cmd_wait_ready(flash, timeout);
  202. if (ret < 0) {
  203. debug("SF: write %s timed out\n",
  204. timeout == SPI_FLASH_PROG_TIMEOUT ?
  205. "program" : "page erase");
  206. return ret;
  207. }
  208. spi_release_bus(spi);
  209. return ret;
  210. }
  211. int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
  212. {
  213. u32 erase_size, erase_addr;
  214. u8 cmd[SPI_FLASH_CMD_LEN];
  215. int ret = -1;
  216. erase_size = flash->erase_size;
  217. if (offset % erase_size || len % erase_size) {
  218. debug("SF: Erase offset/length not multiple of erase size\n");
  219. return -1;
  220. }
  221. if (flash->flash_is_locked) {
  222. if (flash->flash_is_locked(flash, offset, len) > 0) {
  223. printf("offset 0x%x is protected and cannot be erased\n",
  224. offset);
  225. return -EINVAL;
  226. }
  227. }
  228. cmd[0] = flash->erase_cmd;
  229. while (len) {
  230. erase_addr = offset;
  231. #ifdef CONFIG_SF_DUAL_FLASH
  232. if (flash->dual_flash > SF_SINGLE_FLASH)
  233. spi_flash_dual_flash(flash, &erase_addr);
  234. #endif
  235. #ifdef CONFIG_SPI_FLASH_BAR
  236. ret = spi_flash_write_bank(flash, erase_addr);
  237. if (ret < 0)
  238. return ret;
  239. #endif
  240. spi_flash_addr(erase_addr, cmd);
  241. debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
  242. cmd[2], cmd[3], erase_addr);
  243. ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
  244. if (ret < 0) {
  245. debug("SF: erase failed\n");
  246. break;
  247. }
  248. offset += erase_size;
  249. len -= erase_size;
  250. }
  251. return ret;
  252. }
  253. int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
  254. size_t len, const void *buf)
  255. {
  256. unsigned long byte_addr, page_size;
  257. u32 write_addr;
  258. size_t chunk_len, actual;
  259. u8 cmd[SPI_FLASH_CMD_LEN];
  260. int ret = -1;
  261. page_size = flash->page_size;
  262. if (flash->flash_is_locked) {
  263. if (flash->flash_is_locked(flash, offset, len) > 0) {
  264. printf("offset 0x%x is protected and cannot be written\n",
  265. offset);
  266. return -EINVAL;
  267. }
  268. }
  269. cmd[0] = flash->write_cmd;
  270. for (actual = 0; actual < len; actual += chunk_len) {
  271. write_addr = offset;
  272. #ifdef CONFIG_SF_DUAL_FLASH
  273. if (flash->dual_flash > SF_SINGLE_FLASH)
  274. spi_flash_dual_flash(flash, &write_addr);
  275. #endif
  276. #ifdef CONFIG_SPI_FLASH_BAR
  277. ret = spi_flash_write_bank(flash, write_addr);
  278. if (ret < 0)
  279. return ret;
  280. #endif
  281. byte_addr = offset % page_size;
  282. chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
  283. if (flash->spi->max_write_size)
  284. chunk_len = min(chunk_len,
  285. (size_t)flash->spi->max_write_size);
  286. spi_flash_addr(write_addr, cmd);
  287. debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
  288. buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
  289. ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
  290. buf + actual, chunk_len);
  291. if (ret < 0) {
  292. debug("SF: write failed\n");
  293. break;
  294. }
  295. offset += chunk_len;
  296. }
  297. return ret;
  298. }
  299. int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
  300. size_t cmd_len, void *data, size_t data_len)
  301. {
  302. struct spi_slave *spi = flash->spi;
  303. int ret;
  304. ret = spi_claim_bus(flash->spi);
  305. if (ret) {
  306. debug("SF: unable to claim SPI bus\n");
  307. return ret;
  308. }
  309. ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
  310. if (ret < 0) {
  311. debug("SF: read cmd failed\n");
  312. return ret;
  313. }
  314. spi_release_bus(spi);
  315. return ret;
  316. }
  317. void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len)
  318. {
  319. memcpy(data, offset, len);
  320. }
  321. int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
  322. size_t len, void *data)
  323. {
  324. u8 *cmd, cmdsz;
  325. u32 remain_len, read_len, read_addr;
  326. int bank_sel = 0;
  327. int ret = -1;
  328. /* Handle memory-mapped SPI */
  329. if (flash->memory_map) {
  330. ret = spi_claim_bus(flash->spi);
  331. if (ret) {
  332. debug("SF: unable to claim SPI bus\n");
  333. return ret;
  334. }
  335. spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
  336. spi_flash_copy_mmap(data, flash->memory_map + offset, len);
  337. spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
  338. spi_release_bus(flash->spi);
  339. return 0;
  340. }
  341. cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
  342. cmd = calloc(1, cmdsz);
  343. if (!cmd) {
  344. debug("SF: Failed to allocate cmd\n");
  345. return -ENOMEM;
  346. }
  347. cmd[0] = flash->read_cmd;
  348. while (len) {
  349. read_addr = offset;
  350. #ifdef CONFIG_SF_DUAL_FLASH
  351. if (flash->dual_flash > SF_SINGLE_FLASH)
  352. spi_flash_dual_flash(flash, &read_addr);
  353. #endif
  354. #ifdef CONFIG_SPI_FLASH_BAR
  355. ret = spi_flash_write_bank(flash, read_addr);
  356. if (ret < 0)
  357. return ret;
  358. bank_sel = flash->bank_curr;
  359. #endif
  360. remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
  361. (bank_sel + 1)) - offset;
  362. if (len < remain_len)
  363. read_len = len;
  364. else
  365. read_len = remain_len;
  366. spi_flash_addr(read_addr, cmd);
  367. ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
  368. if (ret < 0) {
  369. debug("SF: read failed\n");
  370. break;
  371. }
  372. offset += read_len;
  373. len -= read_len;
  374. data += read_len;
  375. }
  376. free(cmd);
  377. return ret;
  378. }
  379. #ifdef CONFIG_SPI_FLASH_SST
  380. static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
  381. {
  382. int ret;
  383. u8 cmd[4] = {
  384. CMD_SST_BP,
  385. offset >> 16,
  386. offset >> 8,
  387. offset,
  388. };
  389. debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
  390. spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
  391. ret = spi_flash_cmd_write_enable(flash);
  392. if (ret)
  393. return ret;
  394. ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
  395. if (ret)
  396. return ret;
  397. return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
  398. }
  399. int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
  400. const void *buf)
  401. {
  402. size_t actual, cmd_len;
  403. int ret;
  404. u8 cmd[4];
  405. ret = spi_claim_bus(flash->spi);
  406. if (ret) {
  407. debug("SF: Unable to claim SPI bus\n");
  408. return ret;
  409. }
  410. /* If the data is not word aligned, write out leading single byte */
  411. actual = offset % 2;
  412. if (actual) {
  413. ret = sst_byte_write(flash, offset, buf);
  414. if (ret)
  415. goto done;
  416. }
  417. offset += actual;
  418. ret = spi_flash_cmd_write_enable(flash);
  419. if (ret)
  420. goto done;
  421. cmd_len = 4;
  422. cmd[0] = CMD_SST_AAI_WP;
  423. cmd[1] = offset >> 16;
  424. cmd[2] = offset >> 8;
  425. cmd[3] = offset;
  426. for (; actual < len - 1; actual += 2) {
  427. debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
  428. spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
  429. cmd[0], offset);
  430. ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
  431. buf + actual, 2);
  432. if (ret) {
  433. debug("SF: sst word program failed\n");
  434. break;
  435. }
  436. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
  437. if (ret)
  438. break;
  439. cmd_len = 1;
  440. offset += 2;
  441. }
  442. if (!ret)
  443. ret = spi_flash_cmd_write_disable(flash);
  444. /* If there is a single trailing byte, write it out */
  445. if (!ret && actual != len)
  446. ret = sst_byte_write(flash, offset, buf + actual);
  447. done:
  448. debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
  449. ret ? "failure" : "success", len, offset - actual);
  450. spi_release_bus(flash->spi);
  451. return ret;
  452. }
  453. int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
  454. const void *buf)
  455. {
  456. size_t actual;
  457. int ret;
  458. ret = spi_claim_bus(flash->spi);
  459. if (ret) {
  460. debug("SF: Unable to claim SPI bus\n");
  461. return ret;
  462. }
  463. for (actual = 0; actual < len; actual++) {
  464. ret = sst_byte_write(flash, offset, buf + actual);
  465. if (ret) {
  466. debug("SF: sst byte program failed\n");
  467. break;
  468. }
  469. offset++;
  470. }
  471. if (!ret)
  472. ret = spi_flash_cmd_write_disable(flash);
  473. debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
  474. ret ? "failure" : "success", len, offset - actual);
  475. spi_release_bus(flash->spi);
  476. return ret;
  477. }
  478. #endif
  479. #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
  480. static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
  481. u32 *len)
  482. {
  483. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  484. int shift = ffs(mask) - 1;
  485. int pow;
  486. if (!(sr & mask)) {
  487. /* No protection */
  488. *ofs = 0;
  489. *len = 0;
  490. } else {
  491. pow = ((sr & mask) ^ mask) >> shift;
  492. *len = flash->size >> pow;
  493. *ofs = flash->size - *len;
  494. }
  495. }
  496. /*
  497. * Return 1 if the entire region is locked, 0 otherwise
  498. */
  499. static int stm_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len,
  500. u8 sr)
  501. {
  502. loff_t lock_offs;
  503. u32 lock_len;
  504. stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
  505. return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
  506. }
  507. /*
  508. * Check if a region of the flash is (completely) locked. See stm_lock() for
  509. * more info.
  510. *
  511. * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
  512. * negative on errors.
  513. */
  514. int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
  515. {
  516. int status;
  517. u8 sr;
  518. status = spi_flash_cmd_read_status(flash, &sr);
  519. if (status < 0)
  520. return status;
  521. return stm_is_locked_sr(flash, ofs, len, sr);
  522. }
  523. /*
  524. * Lock a region of the flash. Compatible with ST Micro and similar flash.
  525. * Supports only the block protection bits BP{0,1,2} in the status register
  526. * (SR). Does not support these features found in newer SR bitfields:
  527. * - TB: top/bottom protect - only handle TB=0 (top protect)
  528. * - SEC: sector/block protect - only handle SEC=0 (block protect)
  529. * - CMP: complement protect - only support CMP=0 (range is not complemented)
  530. *
  531. * Sample table portion for 8MB flash (Winbond w25q64fw):
  532. *
  533. * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
  534. * --------------------------------------------------------------------------
  535. * X | X | 0 | 0 | 0 | NONE | NONE
  536. * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
  537. * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
  538. * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
  539. * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
  540. * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
  541. * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
  542. * X | X | 1 | 1 | 1 | 8 MB | ALL
  543. *
  544. * Returns negative on errors, 0 on success.
  545. */
  546. int stm_lock(struct spi_flash *flash, u32 ofs, size_t len)
  547. {
  548. u8 status_old, status_new;
  549. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  550. u8 shift = ffs(mask) - 1, pow, val;
  551. int ret;
  552. ret = spi_flash_cmd_read_status(flash, &status_old);
  553. if (ret < 0)
  554. return ret;
  555. /* SPI NOR always locks to the end */
  556. if (ofs + len != flash->size) {
  557. /* Does combined region extend to end? */
  558. if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len,
  559. status_old))
  560. return -EINVAL;
  561. len = flash->size - ofs;
  562. }
  563. /*
  564. * Need smallest pow such that:
  565. *
  566. * 1 / (2^pow) <= (len / size)
  567. *
  568. * so (assuming power-of-2 size) we do:
  569. *
  570. * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
  571. */
  572. pow = ilog2(flash->size) - ilog2(len);
  573. val = mask - (pow << shift);
  574. if (val & ~mask)
  575. return -EINVAL;
  576. /* Don't "lock" with no region! */
  577. if (!(val & mask))
  578. return -EINVAL;
  579. status_new = (status_old & ~mask) | val;
  580. /* Only modify protection if it will not unlock other areas */
  581. if ((status_new & mask) <= (status_old & mask))
  582. return -EINVAL;
  583. spi_flash_cmd_write_status(flash, status_new);
  584. return 0;
  585. }
  586. /*
  587. * Unlock a region of the flash. See stm_lock() for more info
  588. *
  589. * Returns negative on errors, 0 on success.
  590. */
  591. int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
  592. {
  593. uint8_t status_old, status_new;
  594. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  595. u8 shift = ffs(mask) - 1, pow, val;
  596. int ret;
  597. ret = spi_flash_cmd_read_status(flash, &status_old);
  598. if (ret < 0)
  599. return ret;
  600. /* Cannot unlock; would unlock larger region than requested */
  601. if (stm_is_locked_sr(flash, status_old, ofs - flash->erase_size,
  602. flash->erase_size))
  603. return -EINVAL;
  604. /*
  605. * Need largest pow such that:
  606. *
  607. * 1 / (2^pow) >= (len / size)
  608. *
  609. * so (assuming power-of-2 size) we do:
  610. *
  611. * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
  612. */
  613. pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len));
  614. if (ofs + len == flash->size) {
  615. val = 0; /* fully unlocked */
  616. } else {
  617. val = mask - (pow << shift);
  618. /* Some power-of-two sizes are not supported */
  619. if (val & ~mask)
  620. return -EINVAL;
  621. }
  622. status_new = (status_old & ~mask) | val;
  623. /* Only modify protection if it will not lock other areas */
  624. if ((status_new & mask) >= (status_old & mask))
  625. return -EINVAL;
  626. spi_flash_cmd_write_status(flash, status_new);
  627. return 0;
  628. }
  629. #endif