Dinh Nguyen a45526aaa0 arm: socfpga: set the mpuclk divider in the Altera group register %!s(int64=8) %!d(string=hai) anos
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base_addr_a10.h 5a7152e4fd ARM: socfpga: arria10: add base address map for Arria10 %!s(int64=9) %!d(string=hai) anos
base_addr_ac5.h 871c24bc50 ARM: socfpga: rename the cyclone5 and arria5 base address file %!s(int64=9) %!d(string=hai) anos
boot0.h beee6a3083 ARM: socfpga: Add boot0 hook to prevent SPL corruption %!s(int64=8) %!d(string=hai) anos
clock_manager.h a45526aaa0 arm: socfpga: set the mpuclk divider in the Altera group register %!s(int64=8) %!d(string=hai) anos
fpga_manager.h 30088b0997 ARM: socfpga: move SoC headers to mach-socfpga/include/mach %!s(int64=10) %!d(string=hai) anos
freeze_controller.h 30088b0997 ARM: socfpga: move SoC headers to mach-socfpga/include/mach %!s(int64=10) %!d(string=hai) anos
gpio.h 30088b0997 ARM: socfpga: move SoC headers to mach-socfpga/include/mach %!s(int64=10) %!d(string=hai) anos
nic301.h 30088b0997 ARM: socfpga: move SoC headers to mach-socfpga/include/mach %!s(int64=10) %!d(string=hai) anos
reset_manager.h f2f3782ead arm: socfpga: Define NAND reset bit %!s(int64=9) %!d(string=hai) anos
scan_manager.h bd0f5a91f3 arm: socfpga: scan: Add code to get FPGA ID %!s(int64=9) %!d(string=hai) anos
scu.h 30088b0997 ARM: socfpga: move SoC headers to mach-socfpga/include/mach %!s(int64=10) %!d(string=hai) anos
sdram.h 89a54abf1b ddr: altera: Configuring SDRAM extra cycles timing parameters %!s(int64=8) %!d(string=hai) anos
system_manager.h a1684b6105 arm: socfpga: fix up a questionable macro for SDMMC %!s(int64=9) %!d(string=hai) anos
timer.h 30088b0997 ARM: socfpga: move SoC headers to mach-socfpga/include/mach %!s(int64=10) %!d(string=hai) anos