Kconfig 4.2 KB

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  1. if ARCH_SOCFPGA
  2. config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
  3. default 0xa2
  4. config TARGET_SOCFPGA_ARRIA5
  5. bool
  6. select TARGET_SOCFPGA_GEN5
  7. config TARGET_SOCFPGA_ARRIA10
  8. bool
  9. select ALTERA_SDRAM
  10. select SPL_BOARD_INIT if SPL
  11. select CLK
  12. select SPL_CLK if SPL
  13. select DM_I2C
  14. select DM_RESET
  15. select SPL_DM_RESET if SPL
  16. select REGMAP
  17. select SPL_REGMAP if SPL
  18. select SYSCON
  19. select SPL_SYSCON if SPL
  20. select ETH_DESIGNWARE_SOCFPGA
  21. config TARGET_SOCFPGA_CYCLONE5
  22. bool
  23. select TARGET_SOCFPGA_GEN5
  24. config TARGET_SOCFPGA_GEN5
  25. bool
  26. select ALTERA_SDRAM
  27. config TARGET_SOCFPGA_STRATIX10
  28. bool
  29. select ARMV8_MULTIENTRY
  30. select ARMV8_SET_SMPEN
  31. select ARMV8_SPIN_TABLE
  32. choice
  33. prompt "Altera SOCFPGA board select"
  34. optional
  35. config TARGET_SOCFPGA_ARRIA10_SOCDK
  36. bool "Altera SOCFPGA SoCDK (Arria 10)"
  37. select TARGET_SOCFPGA_ARRIA10
  38. config TARGET_SOCFPGA_ARRIA5_SOCDK
  39. bool "Altera SOCFPGA SoCDK (Arria V)"
  40. select TARGET_SOCFPGA_ARRIA5
  41. config TARGET_SOCFPGA_CYCLONE5_SOCDK
  42. bool "Altera SOCFPGA SoCDK (Cyclone V)"
  43. select TARGET_SOCFPGA_CYCLONE5
  44. config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  45. bool "Devboards DBM-SoC1 (Cyclone V)"
  46. select TARGET_SOCFPGA_CYCLONE5
  47. config TARGET_SOCFPGA_EBV_SOCRATES
  48. bool "EBV SoCrates (Cyclone V)"
  49. select TARGET_SOCFPGA_CYCLONE5
  50. config TARGET_SOCFPGA_IS1
  51. bool "IS1 (Cyclone V)"
  52. select TARGET_SOCFPGA_CYCLONE5
  53. config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  54. bool "samtec VIN|ING FPGA (Cyclone V)"
  55. select BOARD_LATE_INIT
  56. select TARGET_SOCFPGA_CYCLONE5
  57. config TARGET_SOCFPGA_SR1500
  58. bool "SR1500 (Cyclone V)"
  59. select TARGET_SOCFPGA_CYCLONE5
  60. config TARGET_SOCFPGA_STRATIX10_SOCDK
  61. bool "Intel SOCFPGA SoCDK (Stratix 10)"
  62. select TARGET_SOCFPGA_STRATIX10
  63. config TARGET_SOCFPGA_TERASIC_DE0_NANO
  64. bool "Terasic DE0-Nano-Atlas (Cyclone V)"
  65. select TARGET_SOCFPGA_CYCLONE5
  66. config TARGET_SOCFPGA_TERASIC_DE10_NANO
  67. bool "Terasic DE10-Nano (Cyclone V)"
  68. select TARGET_SOCFPGA_CYCLONE5
  69. config TARGET_SOCFPGA_TERASIC_DE1_SOC
  70. bool "Terasic DE1-SoC (Cyclone V)"
  71. select TARGET_SOCFPGA_CYCLONE5
  72. config TARGET_SOCFPGA_TERASIC_SOCKIT
  73. bool "Terasic SoCkit (Cyclone V)"
  74. select TARGET_SOCFPGA_CYCLONE5
  75. endchoice
  76. config SYS_BOARD
  77. default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  78. default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
  79. default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  80. default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  81. default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  82. default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  83. default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  84. default "is1" if TARGET_SOCFPGA_IS1
  85. default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  86. default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  87. default "sr1500" if TARGET_SOCFPGA_SR1500
  88. default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
  89. default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  90. config SYS_VENDOR
  91. default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
  92. default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
  93. default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  94. default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
  95. default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  96. default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
  97. default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  98. default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  99. default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  100. default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  101. default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
  102. config SYS_SOC
  103. default "socfpga"
  104. config SYS_CONFIG_NAME
  105. default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  106. default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
  107. default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  108. default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  109. default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  110. default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  111. default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  112. default "socfpga_is1" if TARGET_SOCFPGA_IS1
  113. default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  114. default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  115. default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
  116. default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
  117. default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  118. endif