cpu.c 16 KB

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  1. /*
  2. * (C) Copyright 2000-2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * m8xx.c
  25. *
  26. * CPU specific code
  27. *
  28. * written or collected and sometimes rewritten by
  29. * Magnus Damm <damm@bitsmart.com>
  30. *
  31. * minor modifications by
  32. * Wolfgang Denk <wd@denx.de>
  33. */
  34. #include <common.h>
  35. #include <watchdog.h>
  36. #include <command.h>
  37. #include <mpc8xx.h>
  38. #include <commproc.h>
  39. #include <netdev.h>
  40. #include <asm/cache.h>
  41. #include <linux/compiler.h>
  42. #include <asm/io.h>
  43. #if defined(CONFIG_OF_LIBFDT)
  44. #include <libfdt.h>
  45. #include <fdt_support.h>
  46. #endif
  47. DECLARE_GLOBAL_DATA_PTR;
  48. static char *cpu_warning = "\n " \
  49. "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
  50. #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
  51. !defined(CONFIG_MPC862))
  52. static int check_CPU (long clock, uint pvr, uint immr)
  53. {
  54. char *id_str =
  55. # if defined(CONFIG_MPC855)
  56. "PC855";
  57. # elif defined(CONFIG_MPC860P)
  58. "PC860P";
  59. # else
  60. NULL;
  61. # endif
  62. volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  63. uint k, m;
  64. char buf[32];
  65. char pre = 'X';
  66. char *mid = "xx";
  67. char *suf;
  68. /* the highest 16 bits should be 0x0050 for a 860 */
  69. if ((pvr >> 16) != 0x0050)
  70. return -1;
  71. k = (immr << 16) |
  72. immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
  73. m = 0;
  74. suf = "";
  75. /*
  76. * Some boards use sockets so different CPUs can be used.
  77. * We have to check chip version in run time.
  78. */
  79. switch (k) {
  80. case 0x00020001: pre = 'P'; break;
  81. case 0x00030001: break;
  82. case 0x00120003: suf = "A"; break;
  83. case 0x00130003: suf = "A3"; break;
  84. case 0x00200004: suf = "B"; break;
  85. case 0x00300004: suf = "C"; break;
  86. case 0x00310004: suf = "C1"; m = 1; break;
  87. case 0x00200064: mid = "SR"; suf = "B"; break;
  88. case 0x00300065: mid = "SR"; suf = "C"; break;
  89. case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
  90. case 0x05010000: suf = "D3"; m = 1; break;
  91. case 0x05020000: suf = "D4"; m = 1; break;
  92. /* this value is not documented anywhere */
  93. case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
  94. /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
  95. case 0x08010004: /* Rev. A.0 */
  96. suf = "A";
  97. /* fall through */
  98. case 0x08000003: /* Rev. 0.3 */
  99. pre = 'M'; m = 1;
  100. if (id_str == NULL)
  101. id_str =
  102. # if defined(CONFIG_MPC852T)
  103. "PC852T";
  104. # elif defined(CONFIG_MPC859T)
  105. "PC859T";
  106. # elif defined(CONFIG_MPC859DSL)
  107. "PC859DSL";
  108. # elif defined(CONFIG_MPC866T)
  109. "PC866T";
  110. # else
  111. "PC866x"; /* Unknown chip from MPC866 family */
  112. # endif
  113. break;
  114. case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
  115. if (id_str == NULL)
  116. id_str = "PC885"; /* 870/875/880/885 */
  117. break;
  118. default: suf = NULL; break;
  119. }
  120. if (id_str == NULL)
  121. id_str = "PC86x"; /* Unknown 86x chip */
  122. if (suf)
  123. printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
  124. else
  125. printf ("unknown M%s (0x%08x)", id_str, k);
  126. #if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX)
  127. printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
  128. strmhz (buf, clock),
  129. CONFIG_SYS_8xx_CPUCLK_MIN / 1000000,
  130. ((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
  131. CONFIG_SYS_8xx_CPUCLK_MAX / 1000000,
  132. ((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
  133. );
  134. #else
  135. printf (" at %s MHz: ", strmhz (buf, clock));
  136. #endif
  137. printf ("%u kB I-Cache %u kB D-Cache",
  138. checkicache () >> 10,
  139. checkdcache () >> 10
  140. );
  141. /* do we have a FEC (860T/P or 852/859/866/885)? */
  142. immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
  143. if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
  144. printf (" FEC present");
  145. }
  146. if (!m) {
  147. puts (cpu_warning);
  148. }
  149. putc ('\n');
  150. #ifdef DEBUG
  151. if(clock != measure_gclk()) {
  152. printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
  153. }
  154. #endif
  155. return 0;
  156. }
  157. #elif defined(CONFIG_MPC862)
  158. static int check_CPU (long clock, uint pvr, uint immr)
  159. {
  160. volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  161. uint k, m;
  162. char buf[32];
  163. char pre = 'X';
  164. __maybe_unused char *mid = "xx";
  165. char *suf;
  166. /* the highest 16 bits should be 0x0050 for a 8xx */
  167. if ((pvr >> 16) != 0x0050)
  168. return -1;
  169. k = (immr << 16) |
  170. immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
  171. m = 0;
  172. switch (k) {
  173. /* this value is not documented anywhere */
  174. case 0x06000000: mid = "P"; suf = "0"; break;
  175. case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
  176. case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
  177. default: suf = NULL; break;
  178. }
  179. #ifndef CONFIG_MPC857
  180. if (suf)
  181. printf ("%cPC862%sZPnn%s", pre, mid, suf);
  182. else
  183. printf ("unknown MPC862 (0x%08x)", k);
  184. #else
  185. if (suf)
  186. printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
  187. else
  188. printf ("unknown MPC857 (0x%08x)", k);
  189. #endif
  190. printf (" at %s MHz:", strmhz (buf, clock));
  191. printf (" %u kB I-Cache", checkicache () >> 10);
  192. printf (" %u kB D-Cache", checkdcache () >> 10);
  193. /* lets check and see if we're running on a 862T (or P?) */
  194. immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
  195. if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
  196. printf (" FEC present");
  197. }
  198. if (!m) {
  199. puts (cpu_warning);
  200. }
  201. putc ('\n');
  202. return 0;
  203. }
  204. #elif defined(CONFIG_MPC823)
  205. static int check_CPU (long clock, uint pvr, uint immr)
  206. {
  207. volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  208. uint k, m;
  209. char buf[32];
  210. char *suf;
  211. /* the highest 16 bits should be 0x0050 for a 8xx */
  212. if ((pvr >> 16) != 0x0050)
  213. return -1;
  214. k = (immr << 16) |
  215. in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
  216. m = 0;
  217. switch (k) {
  218. /* MPC823 */
  219. case 0x20000000: suf = "0"; break;
  220. case 0x20010000: suf = "0.1"; break;
  221. case 0x20020000: suf = "Z2/3"; break;
  222. case 0x20020001: suf = "Z3"; break;
  223. case 0x21000000: suf = "A"; break;
  224. case 0x21010000: suf = "B"; m = 1; break;
  225. case 0x21010001: suf = "B2"; m = 1; break;
  226. /* MPC823E */
  227. case 0x24010000: suf = NULL;
  228. puts ("PPC823EZTnnB2");
  229. m = 1;
  230. break;
  231. default:
  232. suf = NULL;
  233. printf ("unknown MPC823 (0x%08x)", k);
  234. break;
  235. }
  236. if (suf)
  237. printf ("PPC823ZTnn%s", suf);
  238. printf (" at %s MHz:", strmhz (buf, clock));
  239. printf (" %u kB I-Cache", checkicache () >> 10);
  240. printf (" %u kB D-Cache", checkdcache () >> 10);
  241. /* lets check and see if we're running on a 860T (or P?) */
  242. immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
  243. if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
  244. puts (" FEC present");
  245. }
  246. if (!m) {
  247. puts (cpu_warning);
  248. }
  249. putc ('\n');
  250. return 0;
  251. }
  252. #elif defined(CONFIG_MPC850)
  253. static int check_CPU (long clock, uint pvr, uint immr)
  254. {
  255. volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  256. uint k, m;
  257. char buf[32];
  258. /* the highest 16 bits should be 0x0050 for a 8xx */
  259. if ((pvr >> 16) != 0x0050)
  260. return -1;
  261. k = (immr << 16) |
  262. immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
  263. m = 0;
  264. switch (k) {
  265. case 0x20020001:
  266. printf ("XPC850xxZT");
  267. break;
  268. case 0x21000065:
  269. printf ("XPC850xxZTA");
  270. break;
  271. case 0x21010067:
  272. printf ("XPC850xxZTB");
  273. m = 1;
  274. break;
  275. case 0x21020068:
  276. printf ("XPC850xxZTC");
  277. m = 1;
  278. break;
  279. default:
  280. printf ("unknown MPC850 (0x%08x)", k);
  281. }
  282. printf (" at %s MHz:", strmhz (buf, clock));
  283. printf (" %u kB I-Cache", checkicache () >> 10);
  284. printf (" %u kB D-Cache", checkdcache () >> 10);
  285. /* lets check and see if we're running on a 850T (or P?) */
  286. immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
  287. if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
  288. printf (" FEC present");
  289. }
  290. if (!m) {
  291. puts (cpu_warning);
  292. }
  293. putc ('\n');
  294. return 0;
  295. }
  296. #else
  297. #error CPU undefined
  298. #endif
  299. /* ------------------------------------------------------------------------- */
  300. int checkcpu (void)
  301. {
  302. ulong clock = gd->cpu_clk;
  303. uint immr = get_immr (0); /* Return full IMMR contents */
  304. uint pvr = get_pvr ();
  305. puts ("CPU: ");
  306. /* 850 has PARTNUM 20 */
  307. /* 801 has PARTNUM 10 */
  308. return check_CPU (clock, pvr, immr);
  309. }
  310. /* ------------------------------------------------------------------------- */
  311. /* L1 i-cache */
  312. /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
  313. /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
  314. int checkicache (void)
  315. {
  316. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  317. volatile memctl8xx_t *memctl = &immap->im_memctl;
  318. u32 cacheon = rd_ic_cst () & IDC_ENABLED;
  319. #ifdef CONFIG_IP86x
  320. u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
  321. #else
  322. u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
  323. #endif
  324. u32 m;
  325. u32 lines = -1;
  326. wr_ic_cst (IDC_UNALL);
  327. wr_ic_cst (IDC_INVALL);
  328. wr_ic_cst (IDC_DISABLE);
  329. __asm__ volatile ("isync");
  330. while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
  331. wr_ic_adr (k);
  332. wr_ic_cst (IDC_LDLCK);
  333. __asm__ volatile ("isync");
  334. lines++;
  335. k += 0x10; /* the number of bytes in a cacheline */
  336. }
  337. wr_ic_cst (IDC_UNALL);
  338. wr_ic_cst (IDC_INVALL);
  339. if (cacheon)
  340. wr_ic_cst (IDC_ENABLE);
  341. else
  342. wr_ic_cst (IDC_DISABLE);
  343. __asm__ volatile ("isync");
  344. return lines << 4;
  345. };
  346. /* ------------------------------------------------------------------------- */
  347. /* L1 d-cache */
  348. /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
  349. /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
  350. /* call with cache disabled */
  351. int checkdcache (void)
  352. {
  353. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  354. volatile memctl8xx_t *memctl = &immap->im_memctl;
  355. u32 cacheon = rd_dc_cst () & IDC_ENABLED;
  356. #ifdef CONFIG_IP86x
  357. u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
  358. #else
  359. u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
  360. #endif
  361. u32 m;
  362. u32 lines = -1;
  363. wr_dc_cst (IDC_UNALL);
  364. wr_dc_cst (IDC_INVALL);
  365. wr_dc_cst (IDC_DISABLE);
  366. while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
  367. wr_dc_adr (k);
  368. wr_dc_cst (IDC_LDLCK);
  369. lines++;
  370. k += 0x10; /* the number of bytes in a cacheline */
  371. }
  372. wr_dc_cst (IDC_UNALL);
  373. wr_dc_cst (IDC_INVALL);
  374. if (cacheon)
  375. wr_dc_cst (IDC_ENABLE);
  376. else
  377. wr_dc_cst (IDC_DISABLE);
  378. return lines << 4;
  379. };
  380. /* ------------------------------------------------------------------------- */
  381. void upmconfig (uint upm, uint * table, uint size)
  382. {
  383. uint i;
  384. uint addr = 0;
  385. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  386. volatile memctl8xx_t *memctl = &immap->im_memctl;
  387. for (i = 0; i < size; i++) {
  388. memctl->memc_mdr = table[i]; /* (16-15) */
  389. memctl->memc_mcr = addr | upm; /* (16-16) */
  390. addr++;
  391. }
  392. }
  393. /* ------------------------------------------------------------------------- */
  394. #ifndef CONFIG_LWMON
  395. int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  396. {
  397. ulong msr, addr;
  398. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  399. immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
  400. /* Interrupts and MMU off */
  401. __asm__ volatile ("mtspr 81, 0");
  402. __asm__ volatile ("mfmsr %0":"=r" (msr));
  403. msr &= ~0x1030;
  404. __asm__ volatile ("mtmsr %0"::"r" (msr));
  405. /*
  406. * Trying to execute the next instruction at a non-existing address
  407. * should cause a machine check, resulting in reset
  408. */
  409. #ifdef CONFIG_SYS_RESET_ADDRESS
  410. addr = CONFIG_SYS_RESET_ADDRESS;
  411. #else
  412. /*
  413. * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
  414. * - sizeof (ulong) is usually a valid address. Better pick an address
  415. * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
  416. * "(ulong)-1" used to be a good choice for many systems...
  417. */
  418. addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
  419. #endif
  420. ((void (*)(void)) addr) ();
  421. return 1;
  422. }
  423. #else /* CONFIG_LWMON */
  424. /*
  425. * On the LWMON board, the MCLR reset input of the PIC's on the board
  426. * uses a 47K/1n RC combination which has a 47us time constant. The
  427. * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us
  428. * and thus too short to reset the external hardware. So we use the
  429. * watchdog to reset the board.
  430. */
  431. int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  432. {
  433. /* prevent triggering the watchdog */
  434. disable_interrupts ();
  435. /* make sure the watchdog is running */
  436. reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
  437. /* wait for watchdog reset */
  438. while (1) {};
  439. /* NOTREACHED */
  440. return 1;
  441. }
  442. #endif /* CONFIG_LWMON */
  443. /* ------------------------------------------------------------------------- */
  444. /*
  445. * Get timebase clock frequency (like cpu_clk in Hz)
  446. *
  447. * See sections 14.2 and 14.6 of the User's Manual
  448. */
  449. unsigned long get_tbclk (void)
  450. {
  451. uint immr = get_immr (0); /* Return full IMMR contents */
  452. volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
  453. ulong oscclk, factor, pll;
  454. if (immap->im_clkrst.car_sccr & SCCR_TBS) {
  455. return (gd->cpu_clk / 16);
  456. }
  457. pll = immap->im_clkrst.car_plprcr;
  458. #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
  459. /*
  460. * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
  461. * factor is calculated as follows:
  462. *
  463. * MFN
  464. * MFI + -------
  465. * MFD + 1
  466. * factor = -----------------
  467. * (PDF + 1) * 2^S
  468. *
  469. * For older chips, it's just MF field of PLPRCR plus one.
  470. */
  471. if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
  472. factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
  473. (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
  474. } else {
  475. factor = PLPRCR_val(MF)+1;
  476. }
  477. oscclk = gd->cpu_clk / factor;
  478. if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
  479. return (oscclk / 4);
  480. }
  481. return (oscclk / 16);
  482. }
  483. /* ------------------------------------------------------------------------- */
  484. #if defined(CONFIG_WATCHDOG)
  485. void watchdog_reset (void)
  486. {
  487. int re_enable = disable_interrupts ();
  488. reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
  489. if (re_enable)
  490. enable_interrupts ();
  491. }
  492. #endif /* CONFIG_WATCHDOG */
  493. #if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)
  494. void reset_8xx_watchdog (volatile immap_t * immr)
  495. {
  496. # if defined(CONFIG_LWMON)
  497. /*
  498. * The LWMON board uses a MAX6301 Watchdog
  499. * with the trigger pin connected to port PA.7
  500. *
  501. * (The old board version used a MAX706TESA Watchdog, which
  502. * had to be handled exactly the same.)
  503. */
  504. # define WATCHDOG_BIT 0x0100
  505. immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
  506. immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
  507. immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
  508. immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
  509. # elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
  510. /*
  511. * The KUP4 boards uses a TPS3705 Watchdog
  512. * with the trigger pin connected to port PA.5
  513. */
  514. # define WATCHDOG_BIT 0x0400
  515. immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
  516. immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
  517. immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
  518. immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
  519. # else
  520. /*
  521. * All other boards use the MPC8xx Internal Watchdog
  522. */
  523. immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
  524. immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
  525. # endif /* CONFIG_LWMON */
  526. }
  527. #endif /* CONFIG_WATCHDOG */
  528. /*
  529. * Initializes on-chip ethernet controllers.
  530. * to override, implement board_eth_init()
  531. */
  532. int cpu_eth_init(bd_t *bis)
  533. {
  534. #if defined(SCC_ENET) && defined(CONFIG_CMD_NET)
  535. scc_initialize(bis);
  536. #endif
  537. #if defined(FEC_ENET)
  538. fec_initialize(bis);
  539. #endif
  540. return 0;
  541. }