Masahiro Yamada e5a504eb3d MAINTAINERS: comment out invalid maintainers 10 年 前
..
.gitignore 1900d3cfad board: .gitignore: ignore board-specific generated files 11 年 前
Kconfig 461be2f96e kconfig: remove redundant "string" type in arch and board Kconfigs 10 年 前
MAINTAINERS e5a504eb3d MAINTAINERS: comment out invalid maintainers 10 年 前
Makefile ba8dd7755e kbuild: move cmd_mkimage to scripts/Makefile.lib 11 年 前
README.mvblm7 702e6014f1 doc: cleanup - move board READMEs into respective board directories 13 年 前
bootscript fd194f82d1 mpc83xx/mvBLM7: add usb commands and cleanup. 15 年 前
fpga.c 1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files 12 年 前
fpga.h 1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files 12 年 前
mvblm7.c 1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files 12 年 前
mvblm7.h 28887d831b Use common code for Matrix Vision boards 15 年 前
pci.c 1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files 12 年 前

README.mvblm7

Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
-------------------------------------

1. Board Description

The mvBL-M7 is a 120x120mm single board computing platform
with strong focus on stereo image processing applications.

Power Supply is either VDC 12-48V or Pover over Ethernet (PoE)
on any port (requires add-on board).

2 System Components

2.1 CPU
Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
512MByte DDR-II memory @ 133MHz.
8 MByte Nor Flash on local bus.
2 Vitesse VSC8601 RGMII ethernet Phys.
1 USB host controller over ULPI I/F.
2 serial ports. Console running on ttyS0 @ 115200 8N1.
1 SD-Card slot connected to SPI.
System configuration (HRCW) is taken from I2C EEPROM.

2.2 PCI
A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.

2.3 FPGA
Altera Cyclone-II EP2C20/35 with PCI DMA engines.
Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash.

2.3.1 I/O @ FPGA
2x8 Outputs : Infineon High-Side Switches to Main Supply.
2x8 Inputs : Programmable input threshold + trigger capabilities
2 dedicated flash interfaces for illuminator boards.
Cross trigger for chaining several boards.

2.4 I2C
Bus1:
MAX5381 DAC @ 0x60 for 1st digital input threshold.
LM75 @ 0x90 for temperature monitoring.
EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
1st image sensor interface (slave addresses depend on sensor)
Bus2:
MAX5381 DAC @ 0x60 for 2nd digital input threshold.
2nd image sensor interface (slave addresses depend on sensor)

3 Flash layout.

reset vector is 0xFFF00100, i.e. "HIGHBOOT".

FF800000 environment
FF802000 redundant environment
FF804000 u-boot script image
FF806000 redundant u-boot script image
FF808000 device tree blob
FF80A000 redundant device tree blob
FF80C000 tbd.
FF80E000 tbd.
FF810000 kernel
FFC00000 root FS
FFF00000 u-boot
FFF80000 FPGA raw bit file

mtd partitions are propagated to linux kernel via device tree blob.

4 Booting

On startup the bootscript @ FF804000 is executed. This script can be
exchanged easily. Default boot mode is "boot from flash", i.e. system
works stand-alone.

This behaviour depends on some environment variables :

"netboot" : yes ->try dhcp/bootp and boot from network.
A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
DHCP server configuration, e.g. to provide different images to
different devices.

During netboot the system tries to get 3 image files:
1. Kernel - name + data is given during BOOTP.
2. Initrd - name is stored in "initrd_name"
3. device tree blob - name is stored in "dtb_name"
Fallback files are the flash versions.