link.dts 5.1 KB

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  1. /dts-v1/;
  2. /include/ "serial.dtsi"
  3. / {
  4. #address-cells = <1>;
  5. #size-cells = <1>;
  6. model = "Google Link";
  7. compatible = "google,link", "intel,celeron-ivybridge";
  8. config {
  9. silent_console = <0>;
  10. };
  11. gpioa {
  12. compatible = "intel,ich6-gpio";
  13. u-boot,dm-pre-reloc;
  14. reg = <0 0x10>;
  15. bank-name = "A";
  16. };
  17. gpiob {
  18. compatible = "intel,ich6-gpio";
  19. u-boot,dm-pre-reloc;
  20. reg = <0x30 0x10>;
  21. bank-name = "B";
  22. };
  23. gpioc {
  24. compatible = "intel,ich6-gpio";
  25. u-boot,dm-pre-reloc;
  26. reg = <0x40 0x10>;
  27. bank-name = "C";
  28. };
  29. serial {
  30. reg = <0x3f8 8>;
  31. clock-frequency = <115200>;
  32. };
  33. chosen { };
  34. memory { device_type = "memory"; reg = <0 0>; };
  35. spd {
  36. compatible = "memory-spd";
  37. #address-cells = <1>;
  38. #size-cells = <0>;
  39. elpida_4Gb_1600_x16 {
  40. reg = <0>;
  41. data = [92 10 0b 03 04 19 02 02
  42. 03 52 01 08 0a 00 fe 00
  43. 69 78 69 3c 69 11 18 81
  44. 20 08 3c 3c 01 40 83 81
  45. 00 00 00 00 00 00 00 00
  46. 00 00 00 00 00 00 00 00
  47. 00 00 00 00 00 00 00 00
  48. 00 00 00 00 0f 11 42 00
  49. 00 00 00 00 00 00 00 00
  50. 00 00 00 00 00 00 00 00
  51. 00 00 00 00 00 00 00 00
  52. 00 00 00 00 00 00 00 00
  53. 00 00 00 00 00 00 00 00
  54. 00 00 00 00 00 00 00 00
  55. 00 00 00 00 00 02 fe 00
  56. 11 52 00 00 00 07 7f 37
  57. 45 42 4a 32 30 55 47 36
  58. 45 42 55 30 2d 47 4e 2d
  59. 46 20 30 20 02 fe 00 00
  60. 00 00 00 00 00 00 00 00
  61. 00 00 00 00 00 00 00 00
  62. 00 00 00 00 00 00 00 00
  63. 00 00 00 00 00 00 00 00
  64. 00 00 00 00 00 00 00 00
  65. 00 00 00 00 00 00 00 00
  66. 00 00 00 00 00 00 00 00
  67. 00 00 00 00 00 00 00 00
  68. 00 00 00 00 00 00 00 00
  69. 00 00 00 00 00 00 00 00
  70. 00 00 00 00 00 00 00 00
  71. 00 00 00 00 00 00 00 00
  72. 00 00 00 00 00 00 00 00];
  73. };
  74. samsung_4Gb_1600_1.35v_x16 {
  75. reg = <1>;
  76. data = [92 11 0b 03 04 19 02 02
  77. 03 11 01 08 0a 00 fe 00
  78. 69 78 69 3c 69 11 18 81
  79. f0 0a 3c 3c 01 40 83 01
  80. 00 80 00 00 00 00 00 00
  81. 00 00 00 00 00 00 00 00
  82. 00 00 00 00 00 00 00 00
  83. 00 00 00 00 0f 11 02 00
  84. 00 00 00 00 00 00 00 00
  85. 00 00 00 00 00 00 00 00
  86. 00 00 00 00 00 00 00 00
  87. 00 00 00 00 00 00 00 00
  88. 00 00 00 00 00 00 00 00
  89. 00 00 00 00 00 00 00 00
  90. 00 00 00 00 00 80 ce 01
  91. 00 00 00 00 00 00 6a 04
  92. 4d 34 37 31 42 35 36 37
  93. 34 42 48 30 2d 59 4b 30
  94. 20 20 00 00 80 ce 00 00
  95. 00 00 00 00 00 00 00 00
  96. 00 00 00 00 00 00 00 00
  97. 00 00 00 00 00 00 00 00
  98. 00 00 00 00 00 00 00 00
  99. 00 00 00 00 00 00 00 00
  100. 00 00 00 00 00 00 00 00
  101. 00 00 00 00 00 00 00 00
  102. 00 00 00 00 00 00 00 00
  103. 00 00 00 00 00 00 00 00
  104. 00 00 00 00 00 00 00 00
  105. 00 00 00 00 00 00 00 00
  106. 00 00 00 00 00 00 00 00
  107. 00 00 00 00 00 00 00 00];
  108. };
  109. micron_4Gb_1600_1.35v_x16 {
  110. reg = <2>;
  111. data = [92 11 0b 03 04 19 02 02
  112. 03 11 01 08 0a 00 fe 00
  113. 69 78 69 3c 69 11 18 81
  114. 20 08 3c 3c 01 40 83 05
  115. 00 00 00 00 00 00 00 00
  116. 00 00 00 00 00 00 00 00
  117. 00 00 00 00 00 00 00 00
  118. 00 00 00 00 0f 01 02 00
  119. 00 00 00 00 00 00 00 00
  120. 00 00 00 00 00 00 00 00
  121. 00 00 00 00 00 00 00 00
  122. 00 00 00 00 00 00 00 00
  123. 00 00 00 00 00 00 00 00
  124. 00 00 00 00 00 00 00 00
  125. 00 00 00 00 00 80 2c 00
  126. 00 00 00 00 00 00 ad 75
  127. 34 4b 54 46 32 35 36 36
  128. 34 48 5a 2d 31 47 36 45
  129. 31 20 45 31 80 2c 00 00
  130. 00 00 00 00 00 00 00 00
  131. 00 00 00 00 00 00 00 00
  132. 00 00 00 00 00 00 00 00
  133. ff ff ff ff ff ff ff ff
  134. ff ff ff ff ff ff ff ff
  135. ff ff ff ff ff ff ff ff
  136. ff ff ff ff ff ff ff ff
  137. ff ff ff ff ff ff ff ff
  138. ff ff ff ff ff ff ff ff
  139. ff ff ff ff ff ff ff ff
  140. ff ff ff ff ff ff ff ff
  141. ff ff ff ff ff ff ff ff
  142. ff ff ff ff ff ff ff ff];
  143. };
  144. };
  145. spi {
  146. #address-cells = <1>;
  147. #size-cells = <0>;
  148. compatible = "intel,ich9";
  149. spi-flash@0 {
  150. reg = <0>;
  151. compatible = "winbond,w25q64", "spi-flash";
  152. memory-map = <0xff800000 0x00800000>;
  153. };
  154. };
  155. pci {
  156. sata {
  157. compatible = "intel,pantherpoint-ahci";
  158. intel,sata-mode = "ahci";
  159. intel,sata-port-map = <1>;
  160. intel,sata-port0-gen3-tx = <0x00880a7f>;
  161. };
  162. gma {
  163. compatible = "intel,gma";
  164. intel,dp_hotplug = <0 0 0x06>;
  165. intel,panel-port-select = <1>;
  166. intel,panel-power-cycle-delay = <6>;
  167. intel,panel-power-up-delay = <2000>;
  168. intel,panel-power-down-delay = <500>;
  169. intel,panel-power-backlight-on-delay = <2000>;
  170. intel,panel-power-backlight-off-delay = <2000>;
  171. intel,cpu-backlight = <0x00000200>;
  172. intel,pch-backlight = <0x04000000>;
  173. };
  174. lpc {
  175. compatible = "intel,lpc";
  176. #address-cells = <1>;
  177. #size-cells = <1>;
  178. gen-dec = <0x800 0xfc 0x900 0xfc>;
  179. intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
  180. intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
  181. 0x80 0x80 0x80 0x80>;
  182. intel,gpi-routing = <0 0 0 0 0 0 0 2
  183. 1 0 0 0 0 0 0 0>;
  184. /* Enable EC SMI source */
  185. intel,alt-gp-smi-enable = <0x0100>;
  186. cros-ec@200 {
  187. compatible = "google,cros-ec";
  188. reg = <0x204 1 0x200 1 0x880 0x80>;
  189. /* Describes the flash memory within the EC */
  190. #address-cells = <1>;
  191. #size-cells = <1>;
  192. flash@8000000 {
  193. reg = <0x08000000 0x20000>;
  194. erase-value = <0xff>;
  195. };
  196. };
  197. };
  198. };
  199. microcode {
  200. update@0 {
  201. #include "microcode/m12206a7_00000029.dtsi"
  202. };
  203. update@1 {
  204. #include "microcode/m12306a9_0000001b.dtsi"
  205. };
  206. };
  207. };