mxc_ocotp.c 4.7 KB

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  1. /*
  2. * (C) Copyright 2013 ADVANSEE
  3. * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
  4. *
  5. * Based on Dirk Behme's
  6. * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
  7. * which is based on Freescale's
  8. * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
  9. * which is:
  10. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  11. *
  12. * SPDX-License-Identifier: GPL-2.0+
  13. */
  14. #include <common.h>
  15. #include <fuse.h>
  16. #include <asm/errno.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/imx-regs.h>
  20. #define BO_CTRL_WR_UNLOCK 16
  21. #define BM_CTRL_WR_UNLOCK 0xffff0000
  22. #define BV_CTRL_WR_UNLOCK_KEY 0x3e77
  23. #define BM_CTRL_ERROR 0x00000200
  24. #define BM_CTRL_BUSY 0x00000100
  25. #define BO_CTRL_ADDR 0
  26. #define BM_CTRL_ADDR 0x0000007f
  27. #define BO_TIMING_STROBE_READ 16
  28. #define BM_TIMING_STROBE_READ 0x003f0000
  29. #define BV_TIMING_STROBE_READ_NS 37
  30. #define BO_TIMING_RELAX 12
  31. #define BM_TIMING_RELAX 0x0000f000
  32. #define BV_TIMING_RELAX_NS 17
  33. #define BO_TIMING_STROBE_PROG 0
  34. #define BM_TIMING_STROBE_PROG 0x00000fff
  35. #define BV_TIMING_STROBE_PROG_US 10
  36. #define BM_READ_CTRL_READ_FUSE 0x00000001
  37. #define BF(value, field) (((value) << BO_##field) & BM_##field)
  38. #define WRITE_POSTAMBLE_US 2
  39. static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
  40. {
  41. while (readl(&regs->ctrl) & BM_CTRL_BUSY)
  42. udelay(delay_us);
  43. }
  44. static void clear_error(struct ocotp_regs *regs)
  45. {
  46. writel(BM_CTRL_ERROR, &regs->ctrl_clr);
  47. }
  48. static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
  49. int assert, const char *caller)
  50. {
  51. *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  52. if (bank >= ARRAY_SIZE((*regs)->bank) ||
  53. word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
  54. !assert) {
  55. printf("mxc_ocotp %s(): Invalid argument\n", caller);
  56. return -EINVAL;
  57. }
  58. enable_ocotp_clk(1);
  59. wait_busy(*regs, 1);
  60. clear_error(*regs);
  61. return 0;
  62. }
  63. static int finish_access(struct ocotp_regs *regs, const char *caller)
  64. {
  65. u32 err;
  66. err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
  67. clear_error(regs);
  68. if (err) {
  69. printf("mxc_ocotp %s(): Access protect error\n", caller);
  70. return -EIO;
  71. }
  72. return 0;
  73. }
  74. static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
  75. const char *caller)
  76. {
  77. return prepare_access(regs, bank, word, val != NULL, caller);
  78. }
  79. int fuse_read(u32 bank, u32 word, u32 *val)
  80. {
  81. struct ocotp_regs *regs;
  82. int ret;
  83. ret = prepare_read(&regs, bank, word, val, __func__);
  84. if (ret)
  85. return ret;
  86. *val = readl(&regs->bank[bank].fuse_regs[word << 2]);
  87. return finish_access(regs, __func__);
  88. }
  89. static void set_timing(struct ocotp_regs *regs)
  90. {
  91. u32 ipg_clk;
  92. u32 relax, strobe_read, strobe_prog;
  93. u32 timing;
  94. ipg_clk = mxc_get_clock(MXC_IPG_CLK);
  95. relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
  96. strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
  97. 1000000000) + 2 * (relax + 1) - 1;
  98. strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US,
  99. 1000000) + 2 * (relax + 1) - 1;
  100. timing = BF(strobe_read, TIMING_STROBE_READ) |
  101. BF(relax, TIMING_RELAX) |
  102. BF(strobe_prog, TIMING_STROBE_PROG);
  103. clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
  104. BM_TIMING_STROBE_PROG, timing);
  105. }
  106. static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
  107. int write)
  108. {
  109. u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
  110. u32 addr = bank << 3 | word;
  111. set_timing(regs);
  112. clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
  113. BF(wr_unlock, CTRL_WR_UNLOCK) |
  114. BF(addr, CTRL_ADDR));
  115. }
  116. int fuse_sense(u32 bank, u32 word, u32 *val)
  117. {
  118. struct ocotp_regs *regs;
  119. int ret;
  120. ret = prepare_read(&regs, bank, word, val, __func__);
  121. if (ret)
  122. return ret;
  123. setup_direct_access(regs, bank, word, false);
  124. writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
  125. wait_busy(regs, 1);
  126. *val = readl(&regs->read_fuse_data);
  127. return finish_access(regs, __func__);
  128. }
  129. static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
  130. const char *caller)
  131. {
  132. return prepare_access(regs, bank, word, true, caller);
  133. }
  134. int fuse_prog(u32 bank, u32 word, u32 val)
  135. {
  136. struct ocotp_regs *regs;
  137. int ret;
  138. ret = prepare_write(&regs, bank, word, __func__);
  139. if (ret)
  140. return ret;
  141. setup_direct_access(regs, bank, word, true);
  142. writel(val, &regs->data);
  143. wait_busy(regs, BV_TIMING_STROBE_PROG_US);
  144. udelay(WRITE_POSTAMBLE_US);
  145. return finish_access(regs, __func__);
  146. }
  147. int fuse_override(u32 bank, u32 word, u32 val)
  148. {
  149. struct ocotp_regs *regs;
  150. int ret;
  151. ret = prepare_write(&regs, bank, word, __func__);
  152. if (ret)
  153. return ret;
  154. writel(val, &regs->bank[bank].fuse_regs[word << 2]);
  155. return finish_access(regs, __func__);
  156. }