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u-boot
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arch
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arm
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asm
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arch-fsl-layerscape
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ns_access.h

ns_access.h 1.6 KB
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  1. /* SPDX-License-Identifier: GPL-2.0+ */
    2. 

  2. /*
    3. 

  3.  * Copyright 2015 Freescale Semiconductor, Inc.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef __FSL_NS_ACCESS_H_
    7. 

  7. #define __FSL_NS_ACCESS_H_
    8. 

  8. #include <fsl_csu.h>
    9. 

  9. 

  10. enum csu_cslx_ind {
    11. 

  11. 	CSU_CSLX_PCIE2_IO = 0,
    12. 

  12. 	CSU_CSLX_PCIE1_IO,
    13. 

  13. 	CSU_CSLX_MG2TPR_IP,
    14. 

  14. 	CSU_CSLX_IFC_MEM,
    15. 

  15. 	CSU_CSLX_OCRAM,
    16. 

  16. 	CSU_CSLX_GIC,
    17. 

  17. 	CSU_CSLX_PCIE1,
    18. 

  18. 	CSU_CSLX_OCRAM2,
    19. 

  19. 	CSU_CSLX_QSPI_MEM,
    20. 

  20. 	CSU_CSLX_PCIE2,
    21. 

  21. 	CSU_CSLX_SATA,
    22. 

  22. 	CSU_CSLX_USB1,
    23. 

  23. 	CSU_CSLX_QM_BM_SWPORTAL,
    24. 

  24. 	CSU_CSLX_PCIE3 = 16,
    25. 

  25. 	CSU_CSLX_PCIE3_IO,
    26. 

  26. 	CSU_CSLX_USB3 = 20,
    27. 

  27. 	CSU_CSLX_USB2,
    28. 

  28. 	CSU_CSLX_PFE = 23,
    29. 

  29. 	CSU_CSLX_SERDES = 32,
    30. 

  30. 	CSU_CSLX_QDMA,
    31. 

  31. 	CSU_CSLX_LPUART2,
    32. 

  32. 	CSU_CSLX_LPUART1,
    33. 

  33. 	CSU_CSLX_LPUART4,
    34. 

  34. 	CSU_CSLX_LPUART3,
    35. 

  35. 	CSU_CSLX_LPUART6,
    36. 

  36. 	CSU_CSLX_LPUART5,
    37. 

  37. 	CSU_CSLX_DSPI1 = 41,
    38. 

  38. 	CSU_CSLX_QSPI,
    39. 

  39. 	CSU_CSLX_ESDHC,
    40. 

  40. 	CSU_CSLX_IFC = 45,
    41. 

  41. 	CSU_CSLX_I2C1,
    42. 

  42. 	CSU_CSLX_USB_2,
    43. 

  43. 	CSU_CSLX_I2C3 = 48,
    44. 

  44. 	CSU_CSLX_I2C2,
    45. 

  45. 	CSU_CSLX_DUART2 = 50,
    46. 

  46. 	CSU_CSLX_DUART1,
    47. 

  47. 	CSU_CSLX_WDT2,
    48. 

  48. 	CSU_CSLX_WDT1,
    49. 

  49. 	CSU_CSLX_EDMA,
    50. 

  50. 	CSU_CSLX_SYS_CNT,
    51. 

  51. 	CSU_CSLX_DMA_MUX2,
    52. 

  52. 	CSU_CSLX_DMA_MUX1,
    53. 

  53. 	CSU_CSLX_DDR,
    54. 

  54. 	CSU_CSLX_QUICC,
    55. 

  55. 	CSU_CSLX_DCFG_CCU_RCPM = 60,
    56. 

  56. 	CSU_CSLX_SECURE_BOOTROM,
    57. 

  57. 	CSU_CSLX_SFP,
    58. 

  58. 	CSU_CSLX_TMU,
    59. 

  59. 	CSU_CSLX_SECURE_MONITOR,
    60. 

  60. 	CSU_CSLX_SCFG,
    61. 

  61. 	CSU_CSLX_FM = 66,
    62. 

  62. 	CSU_CSLX_SEC5_5,
    63. 

  63. 	CSU_CSLX_BM,
    64. 

  64. 	CSU_CSLX_QM,
    65. 

  65. 	CSU_CSLX_GPIO2 = 70,
    66. 

  66. 	CSU_CSLX_GPIO1,
    67. 

  67. 	CSU_CSLX_GPIO4,
    68. 

  68. 	CSU_CSLX_GPIO3,
    69. 

  69. 	CSU_CSLX_PLATFORM_CONT,
    70. 

  70. 	CSU_CSLX_CSU,
    71. 

  71. 	CSU_CSLX_IIC4 = 77,
    72. 

  72. 	CSU_CSLX_WDT4,
    73. 

  73. 	CSU_CSLX_WDT3,
    74. 

  74. 	CSU_CSLX_ESDHC2 = 80,
    75. 

  75. 	CSU_CSLX_WDT5 = 81,
    76. 

  76. 	CSU_CSLX_SAI2,
    77. 

  77. 	CSU_CSLX_SAI1,
    78. 

  78. 	CSU_CSLX_SAI4,
    79. 

  79. 	CSU_CSLX_SAI3,
    80. 

  80. 	CSU_CSLX_FTM2 = 86,
    81. 

  81. 	CSU_CSLX_FTM1,
    82. 

  82. 	CSU_CSLX_FTM4,
    83. 

  83. 	CSU_CSLX_FTM3,
    84. 

  84. 	CSU_CSLX_FTM6 = 90,
    85. 

  85. 	CSU_CSLX_FTM5,
    86. 

  86. 	CSU_CSLX_FTM8,
    87. 

  87. 	CSU_CSLX_FTM7,
    88. 

  88. 	CSU_CSLX_DSCR = 121,
    89. 

  89. };
    90. 

  90. 

  91. #endif
    92.