Home Explore Help
Sign In
coolsoul
/
u-boot
1
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Tree: 9a6535e05f
Branches Tags
u-boot
/
arch
/
arm
/
mach-uniphier
/
dram
/
ddrphy-ld20-regs.h

ddrphy-ld20-regs.h 2.2 KB
History Raw

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455 
  1. /*
    2. 

  2.  * Copyright (C) 2016 Socionext Inc.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier:	GPL-2.0+
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DDRPHY_LD20_REGS_H
    8. 

  8. #define _DDRPHY_LD20_REGS_H
    9. 

  9. 

  10. #define PHY_REG_SHIFT			2
    11. 

  11. 

  12. #define PHY_SCL_START			(0x40 << (PHY_REG_SHIFT))
    13. 

  13. #define PHY_SCL_DATA_0			(0x41 << (PHY_REG_SHIFT))
    14. 

  14. #define PHY_SCL_DATA_1			(0x42 << (PHY_REG_SHIFT))
    15. 

  15. #define PHY_SCL_LATENCY			(0x43 << (PHY_REG_SHIFT))
    16. 

  16. #define PHY_SCL_CONFIG_1		(0x46 << (PHY_REG_SHIFT))
    17. 

  17. #define PHY_SCL_CONFIG_2		(0x47 << (PHY_REG_SHIFT))
    18. 

  18. #define PHY_PAD_CTRL			(0x48 << (PHY_REG_SHIFT))
    19. 

  19. #define PHY_DLL_RECALIB			(0x49 << (PHY_REG_SHIFT))
    20. 

  20. #define PHY_DLL_ADRCTRL			(0x4A << (PHY_REG_SHIFT))
    21. 

  21. #define PHY_LANE_SEL			(0x4B << (PHY_REG_SHIFT))
    22. 

  22. #define PHY_DLL_TRIM_1			(0x4C << (PHY_REG_SHIFT))
    23. 

  23. #define PHY_DLL_TRIM_2			(0x4D << (PHY_REG_SHIFT))
    24. 

  24. #define PHY_DLL_TRIM_3			(0x4E << (PHY_REG_SHIFT))
    25. 

  25. #define PHY_SCL_MAIN_CLK_DELTA		(0x50 << (PHY_REG_SHIFT))
    26. 

  26. #define PHY_WRLVL_AUTOINC_TRIM		(0x53 << (PHY_REG_SHIFT))
    27. 

  27. #define PHY_WRLVL_DYN_ODT		(0x54 << (PHY_REG_SHIFT))
    28. 

  28. #define PHY_WRLVL_ON_OFF		(0x55 << (PHY_REG_SHIFT))
    29. 

  29. #define PHY_UNQ_ANALOG_DLL_1		(0x57 << (PHY_REG_SHIFT))
    30. 

  30. #define PHY_UNQ_ANALOG_DLL_2		(0x58 << (PHY_REG_SHIFT))
    31. 

  31. #define PHY_DLL_INCR_TRIM_1		(0x59 << (PHY_REG_SHIFT))
    32. 

  32. #define PHY_DLL_INCR_TRIM_3		(0x5A << (PHY_REG_SHIFT))
    33. 

  33. #define PHY_SCL_CONFIG_3		(0x5B << (PHY_REG_SHIFT))
    34. 

  34. #define PHY_UNIQUIFY_TSMC_IO_1		(0x5C << (PHY_REG_SHIFT))
    35. 

  35. #define PHY_SCL_START_ADDR		(0x62 << (PHY_REG_SHIFT))
    36. 

  36. #define PHY_IP_DQ_DQS_BITWISE_TRIM	(0x65 << (PHY_REG_SHIFT))
    37. 

  37. #define PHY_DSCL_CNT			(0x67 << (PHY_REG_SHIFT))
    38. 

  38. #define PHY_OP_DQ_DM_DQS_BITWISE_TRIM	(0x68 << (PHY_REG_SHIFT))
    39. 

  39. #define PHY_DLL_TRIM_CLK		(0x69 << (PHY_REG_SHIFT))
    40. 

  40. #define PHY_DYNAMIC_BIT_LVL		(0x6B << (PHY_REG_SHIFT))
    41. 

  41. #define PHY_SCL_WINDOW_TRIM		(0x6D << (PHY_REG_SHIFT))
    42. 

  42. #define PHY_DISABLE_GATING_FOR_SCL	(0x6E << (PHY_REG_SHIFT))
    43. 

  43. #define PHY_SCL_CONFIG_4		(0x6F << (PHY_REG_SHIFT))
    44. 

  44. #define PHY_DYNAMIC_WRITE_BIT_LVL	(0x70 << (PHY_REG_SHIFT))
    45. 

  45. #define PHY_VREF_TRAINING		(0x72 << (PHY_REG_SHIFT))
    46. 

  46. #define PHY_SCL_GATE_TIMING		(0x78 << (PHY_REG_SHIFT))
    47. 

  47. 

  48. /* MASK */
    49. 

  49. #define MSK_OP_DQ_DM_DQS_BITWISE_TRIM	0x0000007F
    50. 

  50. #define MSK_IP_DQ_DQS_BITWISE_TRIM	0x0000007F
    51. 

  51. #define MSK_OVERRIDE			0x00000080
    52. 

  52. 

  53. #define PHY_BITLVL_DLY_WIDTH		6
    54. 

  54. 

  55. #endif /* _DDRPHY_LD20_REGS_H */
    56.