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- /*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
- #ifndef _SOCFPGA_BASE_ADDRS_H_
- #define _SOCFPGA_BASE_ADDRS_H_
- #define SOCFPGA_L3REGS_ADDRESS 0xff800000
- #define SOCFPGA_UART0_ADDRESS 0xffc02000
- #define SOCFPGA_UART1_ADDRESS 0xffc03000
- #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
- #define SOCFPGA_L4WD0_ADDRESS 0xffd02000
- #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
- #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
- #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
- #define SOCFPGA_SCANMGR_ADDRESS 0xfff02000
- #define SOCFPGA_EMAC0_ADDRESS 0xff700000
- #define SOCFPGA_EMAC1_ADDRESS 0xff702000
- #endif /* _SOCFPGA_BASE_ADDRS_H_ */
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