emif_defs.h 1.9 KB

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  1. /*
  2. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #ifndef _EMIF_DEFS_H_
  23. #define _EMIF_DEFS_H_
  24. #include <asm/arch/hardware.h>
  25. typedef struct {
  26. dv_reg ERCSR;
  27. dv_reg AWCCR;
  28. dv_reg SDBCR;
  29. dv_reg SDRCR;
  30. dv_reg AB1CR;
  31. dv_reg AB2CR;
  32. dv_reg AB3CR;
  33. dv_reg AB4CR;
  34. dv_reg SDTIMR;
  35. dv_reg DDRSR;
  36. dv_reg DDRPHYCR;
  37. dv_reg DDRPHYSR;
  38. dv_reg TOTAR;
  39. dv_reg TOTACTR;
  40. dv_reg DDRPHYID_REV;
  41. dv_reg SDSRETR;
  42. dv_reg EIRR;
  43. dv_reg EIMR;
  44. dv_reg EIMSR;
  45. dv_reg EIMCR;
  46. dv_reg IOCTRLR;
  47. dv_reg IOSTATR;
  48. u_int8_t RSVD0[8];
  49. dv_reg NANDFCR;
  50. dv_reg NANDFSR;
  51. u_int8_t RSVD1[8];
  52. dv_reg NANDFECC[4];
  53. u_int8_t RSVD2[60];
  54. dv_reg NAND4BITECCLOAD;
  55. dv_reg NAND4BITECC1;
  56. dv_reg NAND4BITECC2;
  57. dv_reg NAND4BITECC3;
  58. dv_reg NAND4BITECC4;
  59. dv_reg NANDERRADD1;
  60. dv_reg NANDERRADD2;
  61. dv_reg NANDERRVAL1;
  62. dv_reg NANDERRVAL2;
  63. } emif_registers;
  64. typedef emif_registers *emifregs;
  65. #define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
  66. #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4)
  67. #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2)))
  68. #define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
  69. #define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
  70. #endif