start.S 6.8 KB

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  1. /*
  2. * Startup Code for S3C44B0 CPU-core
  3. *
  4. * (C) Copyright 2004
  5. * DAVE Srl
  6. *
  7. * http://www.dave-tech.it
  8. * http://www.wawnet.biz
  9. * mailto:info@wawnet.biz
  10. *
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. #include <asm-offsets.h>
  30. #include <config.h>
  31. #include <version.h>
  32. /*
  33. * Jump vector table
  34. */
  35. .globl _start
  36. _start: b reset
  37. add pc, pc, #0x0c000000
  38. add pc, pc, #0x0c000000
  39. add pc, pc, #0x0c000000
  40. add pc, pc, #0x0c000000
  41. add pc, pc, #0x0c000000
  42. add pc, pc, #0x0c000000
  43. add pc, pc, #0x0c000000
  44. .balignl 16,0xdeadbeef
  45. /*
  46. *************************************************************************
  47. *
  48. * Startup Code (reset vector)
  49. *
  50. * do important init only if we don't start from memory!
  51. * relocate u-boot to ram
  52. * setup stack
  53. * jump to second stage
  54. *
  55. *************************************************************************
  56. */
  57. .globl _TEXT_BASE
  58. _TEXT_BASE:
  59. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  60. .word CONFIG_SPL_TEXT_BASE
  61. #else
  62. .word CONFIG_SYS_TEXT_BASE
  63. #endif
  64. /*
  65. * These are defined in the board-specific linker script.
  66. * Subtracting _start from them lets the linker put their
  67. * relative position in the executable instead of leaving
  68. * them null.
  69. */
  70. .globl _bss_start_ofs
  71. _bss_start_ofs:
  72. .word __bss_start - _start
  73. .globl _bss_end_ofs
  74. _bss_end_ofs:
  75. .word __bss_end - _start
  76. .globl _end_ofs
  77. _end_ofs:
  78. .word _end - _start
  79. #ifdef CONFIG_USE_IRQ
  80. /* IRQ stack memory (calculated at run-time) */
  81. .globl IRQ_STACK_START
  82. IRQ_STACK_START:
  83. .word 0x0badc0de
  84. /* IRQ stack memory (calculated at run-time) */
  85. .globl FIQ_STACK_START
  86. FIQ_STACK_START:
  87. .word 0x0badc0de
  88. #endif
  89. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  90. .globl IRQ_STACK_START_IN
  91. IRQ_STACK_START_IN:
  92. .word 0x0badc0de
  93. /*
  94. * the actual reset code
  95. */
  96. reset:
  97. /*
  98. * set the cpu to SVC32 mode
  99. */
  100. mrs r0,cpsr
  101. bic r0,r0,#0x1f
  102. orr r0,r0,#0xd3
  103. msr cpsr,r0
  104. /*
  105. * we do sys-critical inits only at reboot,
  106. * not when booting from ram!
  107. */
  108. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  109. bl cpu_init_crit
  110. /*
  111. * before relocating, we have to setup RAM timing
  112. * because memory timing is board-dependend, you will
  113. * find a lowlevel_init.S in your board directory.
  114. */
  115. bl lowlevel_init
  116. #endif
  117. bl _main
  118. /*------------------------------------------------------------------------------*/
  119. /*
  120. * void relocate_code (addr_sp, gd, addr_moni)
  121. *
  122. * This function relocates the monitor code.
  123. */
  124. .globl relocate_code
  125. relocate_code:
  126. mov r4, r0 /* save addr_sp */
  127. mov r5, r1 /* save addr of gd */
  128. mov r6, r2 /* save addr of destination */
  129. adr r0, _start
  130. cmp r0, r6
  131. moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
  132. beq relocate_done /* skip relocation */
  133. mov r1, r6 /* r1 <- scratch for copy_loop */
  134. ldr r3, _bss_start_ofs
  135. add r2, r0, r3 /* r2 <- source end address */
  136. copy_loop:
  137. ldmia r0!, {r9-r10} /* copy from source address [r0] */
  138. stmia r1!, {r9-r10} /* copy to target address [r1] */
  139. cmp r0, r2 /* until source end address [r2] */
  140. blo copy_loop
  141. #ifndef CONFIG_SPL_BUILD
  142. /*
  143. * fix .rel.dyn relocations
  144. */
  145. ldr r0, _TEXT_BASE /* r0 <- Text base */
  146. sub r9, r6, r0 /* r9 <- relocation offset */
  147. ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
  148. add r10, r10, r0 /* r10 <- sym table in FLASH */
  149. ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
  150. add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
  151. ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
  152. add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
  153. fixloop:
  154. ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
  155. add r0, r0, r9 /* r0 <- location to fix up in RAM */
  156. ldr r1, [r2, #4]
  157. and r7, r1, #0xff
  158. cmp r7, #23 /* relative fixup? */
  159. beq fixrel
  160. cmp r7, #2 /* absolute fixup? */
  161. beq fixabs
  162. /* ignore unknown type of fixup */
  163. b fixnext
  164. fixabs:
  165. /* absolute fix: set location to (offset) symbol value */
  166. mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
  167. add r1, r10, r1 /* r1 <- address of symbol in table */
  168. ldr r1, [r1, #4] /* r1 <- symbol value */
  169. add r1, r1, r9 /* r1 <- relocated sym addr */
  170. b fixnext
  171. fixrel:
  172. /* relative fix: increase location by offset */
  173. ldr r1, [r0]
  174. add r1, r1, r9
  175. fixnext:
  176. str r1, [r0]
  177. add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
  178. cmp r2, r3
  179. blo fixloop
  180. #endif
  181. relocate_done:
  182. bx lr
  183. _rel_dyn_start_ofs:
  184. .word __rel_dyn_start - _start
  185. _rel_dyn_end_ofs:
  186. .word __rel_dyn_end - _start
  187. _dynsym_start_ofs:
  188. .word __dynsym_start - _start
  189. .globl c_runtime_cpu_setup
  190. c_runtime_cpu_setup:
  191. bx lr
  192. /*
  193. *************************************************************************
  194. *
  195. * CPU_init_critical registers
  196. *
  197. * setup important registers
  198. * setup memory timing
  199. *
  200. *************************************************************************
  201. */
  202. #define INTCON (0x01c00000+0x200000)
  203. #define INTMSK (0x01c00000+0x20000c)
  204. #define LOCKTIME (0x01c00000+0x18000c)
  205. #define PLLCON (0x01c00000+0x180000)
  206. #define CLKCON (0x01c00000+0x180004)
  207. #define WTCON (0x01c00000+0x130000)
  208. cpu_init_crit:
  209. /* disable watch dog */
  210. ldr r0, =WTCON
  211. ldr r1, =0x0
  212. str r1, [r0]
  213. /*
  214. * mask all IRQs by clearing all bits in the INTMRs
  215. */
  216. ldr r1,=INTMSK
  217. ldr r0, =0x03fffeff
  218. str r0, [r1]
  219. ldr r1, =INTCON
  220. ldr r0, =0x05
  221. str r0, [r1]
  222. /* Set Clock Control Register */
  223. ldr r1, =LOCKTIME
  224. ldrb r0, =800
  225. strb r0, [r1]
  226. ldr r1, =PLLCON
  227. #if CONFIG_S3C44B0_CLOCK_SPEED==66
  228. ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
  229. #elif CONFIG_S3C44B0_CLOCK_SPEED==75
  230. ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
  231. #else
  232. # error CONFIG_S3C44B0_CLOCK_SPEED undefined
  233. #endif
  234. str r0, [r1]
  235. ldr r1,=CLKCON
  236. ldr r0, =0x7ff8
  237. str r0, [r1]
  238. mov pc, lr
  239. /*************************************************/
  240. /* interrupt vectors */
  241. /*************************************************/
  242. real_vectors:
  243. b reset
  244. b undefined_instruction
  245. b software_interrupt
  246. b prefetch_abort
  247. b data_abort
  248. b not_used
  249. b irq
  250. b fiq
  251. /*************************************************/
  252. undefined_instruction:
  253. mov r6, #3
  254. b reset
  255. software_interrupt:
  256. mov r6, #4
  257. b reset
  258. prefetch_abort:
  259. mov r6, #5
  260. b reset
  261. data_abort:
  262. mov r6, #6
  263. b reset
  264. not_used:
  265. /* we *should* never reach this */
  266. mov r6, #7
  267. b reset
  268. irq:
  269. mov r6, #8
  270. b reset
  271. fiq:
  272. mov r6, #9
  273. b reset