dragonboard410c.dts 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Qualcomm APQ8016 based Dragonboard 410C board device tree source
  4. *
  5. * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
  6. */
  7. /dts-v1/;
  8. #include "skeleton64.dtsi"
  9. #include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
  10. / {
  11. model = "Qualcomm Technologies, Inc. Dragonboard 410c";
  12. compatible = "qcom,dragonboard", "qcom,apq8016-sbc";
  13. qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
  14. qcom,board-id = <0x10018 0x0>;
  15. #address-cells = <0x2>;
  16. #size-cells = <0x2>;
  17. memory {
  18. device_type = "memory";
  19. reg = <0 0x80000000 0 0x3da00000>;
  20. };
  21. reserved-memory {
  22. #address-cells = <2>;
  23. #size-cells = <2>;
  24. ranges;
  25. };
  26. chosen {
  27. stdout-path = "/soc/serial@78b0000";
  28. };
  29. soc {
  30. #address-cells = <0x1>;
  31. #size-cells = <0x1>;
  32. ranges = <0x0 0x0 0x0 0xffffffff>;
  33. compatible = "simple-bus";
  34. pinctrl: qcom,tlmm@1000000 {
  35. compatible = "qcom,tlmm-apq8016";
  36. reg = <0x1000000 0x400000>;
  37. blsp1_uart: uart {
  38. function = "blsp1_uart";
  39. pins = "GPIO_4", "GPIO_5";
  40. drive-strength = <DRIVE_STRENGTH_8MA>;
  41. bias-disable;
  42. };
  43. };
  44. clkc: qcom,gcc@1800000 {
  45. compatible = "qcom,gcc-apq8016";
  46. reg = <0x1800000 0x80000>;
  47. #address-cells = <0x1>;
  48. #size-cells = <0x0>;
  49. };
  50. serial@78b0000 {
  51. compatible = "qcom,msm-uartdm-v1.4";
  52. reg = <0x78b0000 0x200>;
  53. clock = <&clkc 4>;
  54. pinctrl-names = "uart";
  55. pinctrl-0 = <&blsp1_uart>;
  56. };
  57. soc_gpios: pinctrl@1000000 {
  58. compatible = "qcom,apq8016-pinctrl";
  59. reg = <0x1000000 0x300000>;
  60. gpio-controller;
  61. gpio-count = <122>;
  62. gpio-bank-name="soc";
  63. #gpio-cells = <1>;
  64. };
  65. ehci@78d9000 {
  66. compatible = "qcom,ehci-host";
  67. reg = <0x78d9000 0x400>;
  68. };
  69. sdhci@07824000 {
  70. compatible = "qcom,sdhci-msm-v4";
  71. reg = <0x7824900 0x11c 0x7824000 0x800>;
  72. bus-width = <0x8>;
  73. index = <0x0>;
  74. non-removable;
  75. clock = <&clkc 0>;
  76. clock-frequency = <100000000>;
  77. };
  78. sdhci@07864000 {
  79. compatible = "qcom,sdhci-msm-v4";
  80. reg = <0x7864900 0x11c 0x7864000 0x800>;
  81. index = <0x1>;
  82. bus-width = <0x4>;
  83. clock = <&clkc 1>;
  84. clock-frequency = <200000000>;
  85. };
  86. wcnss {
  87. bt {
  88. compatible="qcom,wcnss-bt";
  89. };
  90. wifi {
  91. compatible="qcom,wcnss-wlan";
  92. };
  93. };
  94. spmi@200f000 {
  95. compatible = "qcom,spmi-pmic-arb";
  96. reg = <0x200f800 0x200 0x2400000 0x400000 0x2c00000 0x400000>;
  97. #address-cells = <0x1>;
  98. #size-cells = <0x1>;
  99. pmic0: pm8916@0 {
  100. compatible = "qcom,spmi-pmic";
  101. reg = <0x0 0x1>;
  102. #address-cells = <0x1>;
  103. #size-cells = <0x1>;
  104. pm8916_pon: pm8916_pon@800 {
  105. compatible = "qcom,pm8916-pwrkey";
  106. reg = <0x800 0x96>;
  107. #gpio-cells = <2>;
  108. gpio-controller;
  109. };
  110. pm8916_gpios: pm8916_gpios@c000 {
  111. compatible = "qcom,pm8916-gpio";
  112. reg = <0xc000 0x400>;
  113. gpio-controller;
  114. gpio-count = <4>;
  115. #gpio-cells = <2>;
  116. gpio-bank-name="pmic";
  117. };
  118. };
  119. pmic1: pm8916@1 {
  120. compatible = "qcom,spmi-pmic";
  121. reg = <0x1 0x1>;
  122. };
  123. };
  124. };
  125. leds {
  126. compatible = "gpio-leds";
  127. user1 {
  128. label = "green:user1";
  129. gpios = <&soc_gpios 21 0>;
  130. };
  131. user2 {
  132. label = "green:user2";
  133. gpios = <&soc_gpios 120 0>;
  134. };
  135. user3 {
  136. label = "green:user3";
  137. gpios = <&pm8916_gpios 0 0>;
  138. };
  139. user4 {
  140. label = "green:user4";
  141. gpios = <&pm8916_gpios 1 0>;
  142. };
  143. };
  144. };
  145. #include "dragonboard410c-uboot.dtsi"