davinci_i2c.c 8.4 KB

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  1. /*
  2. * TI DaVinci (TMS320DM644x) I2C driver.
  3. *
  4. * (C) Copyright 2012-2014
  5. * Texas Instruments Incorporated, <www.ti.com>
  6. * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
  7. * --------------------------------------------------------
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #include <common.h>
  12. #include <i2c.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/i2c_defs.h>
  15. #include <asm/io.h>
  16. #include "davinci_i2c.h"
  17. #define CHECK_NACK() \
  18. do {\
  19. if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
  20. REG(&(i2c_base->i2c_con)) = 0;\
  21. return 1;\
  22. } \
  23. } while (0)
  24. static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap);
  25. static int wait_for_bus(struct i2c_adapter *adap)
  26. {
  27. struct i2c_regs *i2c_base = davinci_get_base(adap);
  28. int stat, timeout;
  29. REG(&(i2c_base->i2c_stat)) = 0xffff;
  30. for (timeout = 0; timeout < 10; timeout++) {
  31. stat = REG(&(i2c_base->i2c_stat));
  32. if (!((stat) & I2C_STAT_BB)) {
  33. REG(&(i2c_base->i2c_stat)) = 0xffff;
  34. return 0;
  35. }
  36. REG(&(i2c_base->i2c_stat)) = stat;
  37. udelay(50000);
  38. }
  39. REG(&(i2c_base->i2c_stat)) = 0xffff;
  40. return 1;
  41. }
  42. static int poll_i2c_irq(struct i2c_adapter *adap, int mask)
  43. {
  44. struct i2c_regs *i2c_base = davinci_get_base(adap);
  45. int stat, timeout;
  46. for (timeout = 0; timeout < 10; timeout++) {
  47. udelay(1000);
  48. stat = REG(&(i2c_base->i2c_stat));
  49. if (stat & mask)
  50. return stat;
  51. }
  52. REG(&(i2c_base->i2c_stat)) = 0xffff;
  53. return stat | I2C_TIMEOUT;
  54. }
  55. static void flush_rx(struct i2c_adapter *adap)
  56. {
  57. struct i2c_regs *i2c_base = davinci_get_base(adap);
  58. while (1) {
  59. if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
  60. break;
  61. REG(&(i2c_base->i2c_drr));
  62. REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
  63. udelay(1000);
  64. }
  65. }
  66. static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
  67. {
  68. struct i2c_regs *i2c_base = davinci_get_base(adap);
  69. uint32_t div, psc;
  70. psc = 2;
  71. /* SCLL + SCLH */
  72. div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
  73. REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
  74. REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
  75. REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
  76. adap->speed = speed;
  77. return 0;
  78. }
  79. static void davinci_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
  80. {
  81. struct i2c_regs *i2c_base = davinci_get_base(adap);
  82. if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
  83. REG(&(i2c_base->i2c_con)) = 0;
  84. udelay(50000);
  85. }
  86. davinci_i2c_setspeed(adap, speed);
  87. REG(&(i2c_base->i2c_oa)) = slaveadd;
  88. REG(&(i2c_base->i2c_cnt)) = 0;
  89. /* Interrupts must be enabled or I2C module won't work */
  90. REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
  91. I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
  92. /* Now enable I2C controller (get it out of reset) */
  93. REG(&(i2c_base->i2c_con)) = I2C_CON_EN;
  94. udelay(1000);
  95. }
  96. static int davinci_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
  97. {
  98. struct i2c_regs *i2c_base = davinci_get_base(adap);
  99. int rc = 1;
  100. if (chip == REG(&(i2c_base->i2c_oa)))
  101. return rc;
  102. REG(&(i2c_base->i2c_con)) = 0;
  103. if (wait_for_bus(adap))
  104. return 1;
  105. /* try to read one byte from current (or only) address */
  106. REG(&(i2c_base->i2c_cnt)) = 1;
  107. REG(&(i2c_base->i2c_sa)) = chip;
  108. REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
  109. I2C_CON_STP);
  110. udelay(50000);
  111. if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
  112. rc = 0;
  113. flush_rx(adap);
  114. REG(&(i2c_base->i2c_stat)) = 0xffff;
  115. } else {
  116. REG(&(i2c_base->i2c_stat)) = 0xffff;
  117. REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
  118. udelay(20000);
  119. if (wait_for_bus(adap))
  120. return 1;
  121. }
  122. flush_rx(adap);
  123. REG(&(i2c_base->i2c_stat)) = 0xffff;
  124. REG(&(i2c_base->i2c_cnt)) = 0;
  125. return rc;
  126. }
  127. static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
  128. uint32_t addr, int alen, uint8_t *buf, int len)
  129. {
  130. struct i2c_regs *i2c_base = davinci_get_base(adap);
  131. uint32_t tmp;
  132. int i;
  133. if ((alen < 0) || (alen > 2)) {
  134. printf("%s(): bogus address length %x\n", __func__, alen);
  135. return 1;
  136. }
  137. if (wait_for_bus(adap))
  138. return 1;
  139. if (alen != 0) {
  140. /* Start address phase */
  141. tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
  142. REG(&(i2c_base->i2c_cnt)) = alen;
  143. REG(&(i2c_base->i2c_sa)) = chip;
  144. REG(&(i2c_base->i2c_con)) = tmp;
  145. tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
  146. CHECK_NACK();
  147. switch (alen) {
  148. case 2:
  149. /* Send address MSByte */
  150. if (tmp & I2C_STAT_XRDY) {
  151. REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
  152. } else {
  153. REG(&(i2c_base->i2c_con)) = 0;
  154. return 1;
  155. }
  156. tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
  157. CHECK_NACK();
  158. /* No break, fall through */
  159. case 1:
  160. /* Send address LSByte */
  161. if (tmp & I2C_STAT_XRDY) {
  162. REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
  163. } else {
  164. REG(&(i2c_base->i2c_con)) = 0;
  165. return 1;
  166. }
  167. tmp = poll_i2c_irq(adap, I2C_STAT_XRDY |
  168. I2C_STAT_NACK | I2C_STAT_ARDY);
  169. CHECK_NACK();
  170. if (!(tmp & I2C_STAT_ARDY)) {
  171. REG(&(i2c_base->i2c_con)) = 0;
  172. return 1;
  173. }
  174. }
  175. }
  176. /* Address phase is over, now read 'len' bytes and stop */
  177. tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
  178. REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
  179. REG(&(i2c_base->i2c_sa)) = chip;
  180. REG(&(i2c_base->i2c_con)) = tmp;
  181. for (i = 0; i < len; i++) {
  182. tmp = poll_i2c_irq(adap, I2C_STAT_RRDY | I2C_STAT_NACK |
  183. I2C_STAT_ROVR);
  184. CHECK_NACK();
  185. if (tmp & I2C_STAT_RRDY) {
  186. buf[i] = REG(&(i2c_base->i2c_drr));
  187. } else {
  188. REG(&(i2c_base->i2c_con)) = 0;
  189. return 1;
  190. }
  191. }
  192. tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK);
  193. CHECK_NACK();
  194. if (!(tmp & I2C_STAT_SCD)) {
  195. REG(&(i2c_base->i2c_con)) = 0;
  196. return 1;
  197. }
  198. flush_rx(adap);
  199. REG(&(i2c_base->i2c_stat)) = 0xffff;
  200. REG(&(i2c_base->i2c_cnt)) = 0;
  201. REG(&(i2c_base->i2c_con)) = 0;
  202. return 0;
  203. }
  204. static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
  205. uint32_t addr, int alen, uint8_t *buf, int len)
  206. {
  207. struct i2c_regs *i2c_base = davinci_get_base(adap);
  208. uint32_t tmp;
  209. int i;
  210. if ((alen < 0) || (alen > 2)) {
  211. printf("%s(): bogus address length %x\n", __func__, alen);
  212. return 1;
  213. }
  214. if (len < 0) {
  215. printf("%s(): bogus length %x\n", __func__, len);
  216. return 1;
  217. }
  218. if (wait_for_bus(adap))
  219. return 1;
  220. /* Start address phase */
  221. tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
  222. I2C_CON_TRX | I2C_CON_STP;
  223. REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
  224. len & 0xffff : (len & 0xffff) + alen;
  225. REG(&(i2c_base->i2c_sa)) = chip;
  226. REG(&(i2c_base->i2c_con)) = tmp;
  227. switch (alen) {
  228. case 2:
  229. /* Send address MSByte */
  230. tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
  231. CHECK_NACK();
  232. if (tmp & I2C_STAT_XRDY) {
  233. REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
  234. } else {
  235. REG(&(i2c_base->i2c_con)) = 0;
  236. return 1;
  237. }
  238. /* No break, fall through */
  239. case 1:
  240. /* Send address LSByte */
  241. tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
  242. CHECK_NACK();
  243. if (tmp & I2C_STAT_XRDY) {
  244. REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
  245. } else {
  246. REG(&(i2c_base->i2c_con)) = 0;
  247. return 1;
  248. }
  249. }
  250. for (i = 0; i < len; i++) {
  251. tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
  252. CHECK_NACK();
  253. if (tmp & I2C_STAT_XRDY)
  254. REG(&(i2c_base->i2c_dxr)) = buf[i];
  255. else
  256. return 1;
  257. }
  258. tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK);
  259. CHECK_NACK();
  260. if (!(tmp & I2C_STAT_SCD)) {
  261. REG(&(i2c_base->i2c_con)) = 0;
  262. return 1;
  263. }
  264. flush_rx(adap);
  265. REG(&(i2c_base->i2c_stat)) = 0xffff;
  266. REG(&(i2c_base->i2c_cnt)) = 0;
  267. REG(&(i2c_base->i2c_con)) = 0;
  268. return 0;
  269. }
  270. static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
  271. {
  272. switch (adap->hwadapnr) {
  273. #if I2C_BUS_MAX >= 3
  274. case 2:
  275. return (struct i2c_regs *)I2C2_BASE;
  276. #endif
  277. #if I2C_BUS_MAX >= 2
  278. case 1:
  279. return (struct i2c_regs *)I2C1_BASE;
  280. #endif
  281. case 0:
  282. return (struct i2c_regs *)I2C_BASE;
  283. default:
  284. printf("wrong hwadapnr: %d\n", adap->hwadapnr);
  285. }
  286. return NULL;
  287. }
  288. U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe,
  289. davinci_i2c_read, davinci_i2c_write,
  290. davinci_i2c_setspeed,
  291. CONFIG_SYS_DAVINCI_I2C_SPEED,
  292. CONFIG_SYS_DAVINCI_I2C_SLAVE,
  293. 0)
  294. #if I2C_BUS_MAX >= 2
  295. U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe,
  296. davinci_i2c_read, davinci_i2c_write,
  297. davinci_i2c_setspeed,
  298. CONFIG_SYS_DAVINCI_I2C_SPEED1,
  299. CONFIG_SYS_DAVINCI_I2C_SLAVE1,
  300. 1)
  301. #endif
  302. #if I2C_BUS_MAX >= 3
  303. U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe,
  304. davinci_i2c_read, davinci_i2c_write,
  305. davinci_i2c_setspeed,
  306. CONFIG_SYS_DAVINCI_I2C_SPEED2,
  307. CONFIG_SYS_DAVINCI_I2C_SLAVE2,
  308. 2)
  309. #endif