dwc2_udc_otg.c 20 KB

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  1. /*
  2. * drivers/usb/gadget/dwc2_udc_otg.c
  3. * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
  4. *
  5. * Copyright (C) 2008 for Samsung Electronics
  6. *
  7. * BSP Support for Samsung's UDC driver
  8. * available at:
  9. * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  10. *
  11. * State machine bugfixes:
  12. * Marek Szyprowski <m.szyprowski@samsung.com>
  13. *
  14. * Ported to u-boot:
  15. * Marek Szyprowski <m.szyprowski@samsung.com>
  16. * Lukasz Majewski <l.majewski@samsumg.com>
  17. *
  18. * SPDX-License-Identifier: GPL-2.0+
  19. */
  20. #undef DEBUG
  21. #include <common.h>
  22. #include <asm/errno.h>
  23. #include <linux/list.h>
  24. #include <malloc.h>
  25. #include <linux/usb/ch9.h>
  26. #include <linux/usb/gadget.h>
  27. #include <asm/byteorder.h>
  28. #include <asm/unaligned.h>
  29. #include <asm/io.h>
  30. #include <asm/mach-types.h>
  31. #include "dwc2_udc_otg_regs.h"
  32. #include "dwc2_udc_otg_priv.h"
  33. #include <usb/lin_gadget_compat.h>
  34. /***********************************************************/
  35. #define OTG_DMA_MODE 1
  36. #define DEBUG_SETUP 0
  37. #define DEBUG_EP0 0
  38. #define DEBUG_ISR 0
  39. #define DEBUG_OUT_EP 0
  40. #define DEBUG_IN_EP 0
  41. #include <usb/dwc2_udc.h>
  42. #define EP0_CON 0
  43. #define EP_MASK 0xF
  44. static char *state_names[] = {
  45. "WAIT_FOR_SETUP",
  46. "DATA_STATE_XMIT",
  47. "DATA_STATE_NEED_ZLP",
  48. "WAIT_FOR_OUT_STATUS",
  49. "DATA_STATE_RECV",
  50. "WAIT_FOR_COMPLETE",
  51. "WAIT_FOR_OUT_COMPLETE",
  52. "WAIT_FOR_IN_COMPLETE",
  53. "WAIT_FOR_NULL_COMPLETE",
  54. };
  55. #define DRIVER_DESC "DWC2 HS USB OTG Device Driver, (c) Samsung Electronics"
  56. #define DRIVER_VERSION "15 March 2009"
  57. struct dwc2_udc *the_controller;
  58. static const char driver_name[] = "dwc2-udc";
  59. static const char driver_desc[] = DRIVER_DESC;
  60. static const char ep0name[] = "ep0-control";
  61. /* Max packet size*/
  62. static unsigned int ep0_fifo_size = 64;
  63. static unsigned int ep_fifo_size = 512;
  64. static unsigned int ep_fifo_size2 = 1024;
  65. static int reset_available = 1;
  66. static struct usb_ctrlrequest *usb_ctrl;
  67. static dma_addr_t usb_ctrl_dma_addr;
  68. /*
  69. Local declarations.
  70. */
  71. static int dwc2_ep_enable(struct usb_ep *ep,
  72. const struct usb_endpoint_descriptor *);
  73. static int dwc2_ep_disable(struct usb_ep *ep);
  74. static struct usb_request *dwc2_alloc_request(struct usb_ep *ep,
  75. gfp_t gfp_flags);
  76. static void dwc2_free_request(struct usb_ep *ep, struct usb_request *);
  77. static int dwc2_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
  78. static int dwc2_dequeue(struct usb_ep *ep, struct usb_request *);
  79. static int dwc2_fifo_status(struct usb_ep *ep);
  80. static void dwc2_fifo_flush(struct usb_ep *ep);
  81. static void dwc2_ep0_read(struct dwc2_udc *dev);
  82. static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep);
  83. static void dwc2_handle_ep0(struct dwc2_udc *dev);
  84. static int dwc2_ep0_write(struct dwc2_udc *dev);
  85. static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req);
  86. static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status);
  87. static void stop_activity(struct dwc2_udc *dev,
  88. struct usb_gadget_driver *driver);
  89. static int udc_enable(struct dwc2_udc *dev);
  90. static void udc_set_address(struct dwc2_udc *dev, unsigned char address);
  91. static void reconfig_usbd(struct dwc2_udc *dev);
  92. static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed);
  93. static void nuke(struct dwc2_ep *ep, int status);
  94. static int dwc2_udc_set_halt(struct usb_ep *_ep, int value);
  95. static void dwc2_udc_set_nak(struct dwc2_ep *ep);
  96. void set_udc_gadget_private_data(void *p)
  97. {
  98. debug_cond(DEBUG_SETUP != 0,
  99. "%s: the_controller: 0x%p, p: 0x%p\n", __func__,
  100. the_controller, p);
  101. the_controller->gadget.dev.device_data = p;
  102. }
  103. void *get_udc_gadget_private_data(struct usb_gadget *gadget)
  104. {
  105. return gadget->dev.device_data;
  106. }
  107. static struct usb_ep_ops dwc2_ep_ops = {
  108. .enable = dwc2_ep_enable,
  109. .disable = dwc2_ep_disable,
  110. .alloc_request = dwc2_alloc_request,
  111. .free_request = dwc2_free_request,
  112. .queue = dwc2_queue,
  113. .dequeue = dwc2_dequeue,
  114. .set_halt = dwc2_udc_set_halt,
  115. .fifo_status = dwc2_fifo_status,
  116. .fifo_flush = dwc2_fifo_flush,
  117. };
  118. #define create_proc_files() do {} while (0)
  119. #define remove_proc_files() do {} while (0)
  120. /***********************************************************/
  121. void __iomem *regs_otg;
  122. struct dwc2_usbotg_reg *reg;
  123. bool dfu_usb_get_reset(void)
  124. {
  125. return !!(readl(&reg->gintsts) & INT_RESET);
  126. }
  127. __weak void otg_phy_init(struct dwc2_udc *dev) {}
  128. __weak void otg_phy_off(struct dwc2_udc *dev) {}
  129. /***********************************************************/
  130. #include "dwc2_udc_otg_xfer_dma.c"
  131. /*
  132. * udc_disable - disable USB device controller
  133. */
  134. static void udc_disable(struct dwc2_udc *dev)
  135. {
  136. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  137. udc_set_address(dev, 0);
  138. dev->ep0state = WAIT_FOR_SETUP;
  139. dev->gadget.speed = USB_SPEED_UNKNOWN;
  140. dev->usb_address = 0;
  141. otg_phy_off(dev);
  142. }
  143. /*
  144. * udc_reinit - initialize software state
  145. */
  146. static void udc_reinit(struct dwc2_udc *dev)
  147. {
  148. unsigned int i;
  149. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  150. /* device/ep0 records init */
  151. INIT_LIST_HEAD(&dev->gadget.ep_list);
  152. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  153. dev->ep0state = WAIT_FOR_SETUP;
  154. /* basic endpoint records init */
  155. for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
  156. struct dwc2_ep *ep = &dev->ep[i];
  157. if (i != 0)
  158. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  159. ep->desc = 0;
  160. ep->stopped = 0;
  161. INIT_LIST_HEAD(&ep->queue);
  162. ep->pio_irqs = 0;
  163. }
  164. /* the rest was statically initialized, and is read-only */
  165. }
  166. #define BYTES2MAXP(x) (x / 8)
  167. #define MAXP2BYTES(x) (x * 8)
  168. /* until it's enabled, this UDC should be completely invisible
  169. * to any USB host.
  170. */
  171. static int udc_enable(struct dwc2_udc *dev)
  172. {
  173. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  174. otg_phy_init(dev);
  175. reconfig_usbd(dev);
  176. debug_cond(DEBUG_SETUP != 0,
  177. "DWC2 USB 2.0 OTG Controller Core Initialized : 0x%x\n",
  178. readl(&reg->gintmsk));
  179. dev->gadget.speed = USB_SPEED_UNKNOWN;
  180. return 0;
  181. }
  182. /*
  183. Register entry point for the peripheral controller driver.
  184. */
  185. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  186. {
  187. struct dwc2_udc *dev = the_controller;
  188. int retval = 0;
  189. unsigned long flags = 0;
  190. debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
  191. if (!driver
  192. || (driver->speed != USB_SPEED_FULL
  193. && driver->speed != USB_SPEED_HIGH)
  194. || !driver->bind || !driver->disconnect || !driver->setup)
  195. return -EINVAL;
  196. if (!dev)
  197. return -ENODEV;
  198. if (dev->driver)
  199. return -EBUSY;
  200. spin_lock_irqsave(&dev->lock, flags);
  201. /* first hook up the driver ... */
  202. dev->driver = driver;
  203. spin_unlock_irqrestore(&dev->lock, flags);
  204. if (retval) { /* TODO */
  205. printf("target device_add failed, error %d\n", retval);
  206. return retval;
  207. }
  208. retval = driver->bind(&dev->gadget);
  209. if (retval) {
  210. debug_cond(DEBUG_SETUP != 0,
  211. "%s: bind to driver --> error %d\n",
  212. dev->gadget.name, retval);
  213. dev->driver = 0;
  214. return retval;
  215. }
  216. enable_irq(IRQ_OTG);
  217. debug_cond(DEBUG_SETUP != 0,
  218. "Registered gadget driver %s\n", dev->gadget.name);
  219. udc_enable(dev);
  220. return 0;
  221. }
  222. /*
  223. * Unregister entry point for the peripheral controller driver.
  224. */
  225. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  226. {
  227. struct dwc2_udc *dev = the_controller;
  228. unsigned long flags = 0;
  229. if (!dev)
  230. return -ENODEV;
  231. if (!driver || driver != dev->driver)
  232. return -EINVAL;
  233. spin_lock_irqsave(&dev->lock, flags);
  234. dev->driver = 0;
  235. stop_activity(dev, driver);
  236. spin_unlock_irqrestore(&dev->lock, flags);
  237. driver->unbind(&dev->gadget);
  238. disable_irq(IRQ_OTG);
  239. udc_disable(dev);
  240. return 0;
  241. }
  242. /*
  243. * done - retire a request; caller blocked irqs
  244. */
  245. static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status)
  246. {
  247. unsigned int stopped = ep->stopped;
  248. debug("%s: %s %p, req = %p, stopped = %d\n",
  249. __func__, ep->ep.name, ep, &req->req, stopped);
  250. list_del_init(&req->queue);
  251. if (likely(req->req.status == -EINPROGRESS))
  252. req->req.status = status;
  253. else
  254. status = req->req.status;
  255. if (status && status != -ESHUTDOWN) {
  256. debug("complete %s req %p stat %d len %u/%u\n",
  257. ep->ep.name, &req->req, status,
  258. req->req.actual, req->req.length);
  259. }
  260. /* don't modify queue heads during completion callback */
  261. ep->stopped = 1;
  262. #ifdef DEBUG
  263. printf("calling complete callback\n");
  264. {
  265. int i, len = req->req.length;
  266. printf("pkt[%d] = ", req->req.length);
  267. if (len > 64)
  268. len = 64;
  269. for (i = 0; i < len; i++) {
  270. printf("%02x", ((u8 *)req->req.buf)[i]);
  271. if ((i & 7) == 7)
  272. printf(" ");
  273. }
  274. printf("\n");
  275. }
  276. #endif
  277. spin_unlock(&ep->dev->lock);
  278. req->req.complete(&ep->ep, &req->req);
  279. spin_lock(&ep->dev->lock);
  280. debug("callback completed\n");
  281. ep->stopped = stopped;
  282. }
  283. /*
  284. * nuke - dequeue ALL requests
  285. */
  286. static void nuke(struct dwc2_ep *ep, int status)
  287. {
  288. struct dwc2_request *req;
  289. debug("%s: %s %p\n", __func__, ep->ep.name, ep);
  290. /* called with irqs blocked */
  291. while (!list_empty(&ep->queue)) {
  292. req = list_entry(ep->queue.next, struct dwc2_request, queue);
  293. done(ep, req, status);
  294. }
  295. }
  296. static void stop_activity(struct dwc2_udc *dev,
  297. struct usb_gadget_driver *driver)
  298. {
  299. int i;
  300. /* don't disconnect drivers more than once */
  301. if (dev->gadget.speed == USB_SPEED_UNKNOWN)
  302. driver = 0;
  303. dev->gadget.speed = USB_SPEED_UNKNOWN;
  304. /* prevent new request submissions, kill any outstanding requests */
  305. for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
  306. struct dwc2_ep *ep = &dev->ep[i];
  307. ep->stopped = 1;
  308. nuke(ep, -ESHUTDOWN);
  309. }
  310. /* report disconnect; the driver is already quiesced */
  311. if (driver) {
  312. spin_unlock(&dev->lock);
  313. driver->disconnect(&dev->gadget);
  314. spin_lock(&dev->lock);
  315. }
  316. /* re-init driver-visible data structures */
  317. udc_reinit(dev);
  318. }
  319. static void reconfig_usbd(struct dwc2_udc *dev)
  320. {
  321. /* 2. Soft-reset OTG Core and then unreset again. */
  322. int i;
  323. unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
  324. uint32_t dflt_gusbcfg;
  325. debug("Reseting OTG controller\n");
  326. dflt_gusbcfg =
  327. 0<<15 /* PHY Low Power Clock sel*/
  328. |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/
  329. |0x5<<10 /* Turnaround time*/
  330. |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
  331. /* 1:SRP enable] H1= 1,1*/
  332. |0<<7 /* Ulpi DDR sel*/
  333. |0<<6 /* 0: high speed utmi+, 1: full speed serial*/
  334. |0<<4 /* 0: utmi+, 1:ulpi*/
  335. |1<<3 /* phy i/f 0:8bit, 1:16bit*/
  336. |0x7<<0; /* HS/FS Timeout**/
  337. if (dev->pdata->usb_gusbcfg)
  338. dflt_gusbcfg = dev->pdata->usb_gusbcfg;
  339. writel(dflt_gusbcfg, &reg->gusbcfg);
  340. /* 3. Put the OTG device core in the disconnected state.*/
  341. uTemp = readl(&reg->dctl);
  342. uTemp |= SOFT_DISCONNECT;
  343. writel(uTemp, &reg->dctl);
  344. udelay(20);
  345. /* 4. Make the OTG device core exit from the disconnected state.*/
  346. uTemp = readl(&reg->dctl);
  347. uTemp = uTemp & ~SOFT_DISCONNECT;
  348. writel(uTemp, &reg->dctl);
  349. /* 5. Configure OTG Core to initial settings of device mode.*/
  350. /* [][1: full speed(30Mhz) 0:high speed]*/
  351. writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, &reg->dcfg);
  352. mdelay(1);
  353. /* 6. Unmask the core interrupts*/
  354. writel(GINTMSK_INIT, &reg->gintmsk);
  355. /* 7. Set NAK bit of EP0, EP1, EP2*/
  356. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[EP0_CON].doepctl);
  357. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[EP0_CON].diepctl);
  358. for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) {
  359. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[i].doepctl);
  360. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[i].diepctl);
  361. }
  362. /* 8. Unmask EPO interrupts*/
  363. writel(((1 << EP0_CON) << DAINT_OUT_BIT)
  364. | (1 << EP0_CON), &reg->daintmsk);
  365. /* 9. Unmask device OUT EP common interrupts*/
  366. writel(DOEPMSK_INIT, &reg->doepmsk);
  367. /* 10. Unmask device IN EP common interrupts*/
  368. writel(DIEPMSK_INIT, &reg->diepmsk);
  369. /* 11. Set Rx FIFO Size (in 32-bit words) */
  370. writel(RX_FIFO_SIZE >> 2, &reg->grxfsiz);
  371. /* 12. Set Non Periodic Tx FIFO Size */
  372. writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0,
  373. &reg->gnptxfsiz);
  374. for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++)
  375. writel((PTX_FIFO_SIZE >> 2) << 16 |
  376. ((RX_FIFO_SIZE + NPTX_FIFO_SIZE +
  377. PTX_FIFO_SIZE*(i-1)) >> 2) << 0,
  378. &reg->dieptxf[i-1]);
  379. /* Flush the RX FIFO */
  380. writel(RX_FIFO_FLUSH, &reg->grstctl);
  381. while (readl(&reg->grstctl) & RX_FIFO_FLUSH)
  382. debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
  383. /* Flush all the Tx FIFO's */
  384. writel(TX_FIFO_FLUSH_ALL, &reg->grstctl);
  385. writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, &reg->grstctl);
  386. while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
  387. debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
  388. /* 13. Clear NAK bit of EP0, EP1, EP2*/
  389. /* For Slave mode*/
  390. /* EP0: Control OUT */
  391. writel(DEPCTL_EPDIS | DEPCTL_CNAK,
  392. &reg->out_endp[EP0_CON].doepctl);
  393. /* 14. Initialize OTG Link Core.*/
  394. writel(GAHBCFG_INIT, &reg->gahbcfg);
  395. }
  396. static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed)
  397. {
  398. unsigned int ep_ctrl;
  399. int i;
  400. if (speed == USB_SPEED_HIGH) {
  401. ep0_fifo_size = 64;
  402. ep_fifo_size = 512;
  403. ep_fifo_size2 = 1024;
  404. dev->gadget.speed = USB_SPEED_HIGH;
  405. } else {
  406. ep0_fifo_size = 64;
  407. ep_fifo_size = 64;
  408. ep_fifo_size2 = 64;
  409. dev->gadget.speed = USB_SPEED_FULL;
  410. }
  411. dev->ep[0].ep.maxpacket = ep0_fifo_size;
  412. for (i = 1; i < DWC2_MAX_ENDPOINTS; i++)
  413. dev->ep[i].ep.maxpacket = ep_fifo_size;
  414. /* EP0 - Control IN (64 bytes)*/
  415. ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  416. writel(ep_ctrl|(0<<0), &reg->in_endp[EP0_CON].diepctl);
  417. /* EP0 - Control OUT (64 bytes)*/
  418. ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  419. writel(ep_ctrl|(0<<0), &reg->out_endp[EP0_CON].doepctl);
  420. }
  421. static int dwc2_ep_enable(struct usb_ep *_ep,
  422. const struct usb_endpoint_descriptor *desc)
  423. {
  424. struct dwc2_ep *ep;
  425. struct dwc2_udc *dev;
  426. unsigned long flags = 0;
  427. debug("%s: %p\n", __func__, _ep);
  428. ep = container_of(_ep, struct dwc2_ep, ep);
  429. if (!_ep || !desc || ep->desc || _ep->name == ep0name
  430. || desc->bDescriptorType != USB_DT_ENDPOINT
  431. || ep->bEndpointAddress != desc->bEndpointAddress
  432. || ep_maxpacket(ep) <
  433. le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
  434. debug("%s: bad ep or descriptor\n", __func__);
  435. return -EINVAL;
  436. }
  437. /* xfer types must match, except that interrupt ~= bulk */
  438. if (ep->bmAttributes != desc->bmAttributes
  439. && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
  440. && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
  441. debug("%s: %s type mismatch\n", __func__, _ep->name);
  442. return -EINVAL;
  443. }
  444. /* hardware _could_ do smaller, but driver doesn't */
  445. if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK &&
  446. le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) >
  447. ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) {
  448. debug("%s: bad %s maxpacket\n", __func__, _ep->name);
  449. return -ERANGE;
  450. }
  451. dev = ep->dev;
  452. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
  453. debug("%s: bogus device state\n", __func__);
  454. return -ESHUTDOWN;
  455. }
  456. ep->stopped = 0;
  457. ep->desc = desc;
  458. ep->pio_irqs = 0;
  459. ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
  460. /* Reset halt state */
  461. dwc2_udc_set_nak(ep);
  462. dwc2_udc_set_halt(_ep, 0);
  463. spin_lock_irqsave(&ep->dev->lock, flags);
  464. dwc2_udc_ep_activate(ep);
  465. spin_unlock_irqrestore(&ep->dev->lock, flags);
  466. debug("%s: enabled %s, stopped = %d, maxpacket = %d\n",
  467. __func__, _ep->name, ep->stopped, ep->ep.maxpacket);
  468. return 0;
  469. }
  470. /*
  471. * Disable EP
  472. */
  473. static int dwc2_ep_disable(struct usb_ep *_ep)
  474. {
  475. struct dwc2_ep *ep;
  476. unsigned long flags = 0;
  477. debug("%s: %p\n", __func__, _ep);
  478. ep = container_of(_ep, struct dwc2_ep, ep);
  479. if (!_ep || !ep->desc) {
  480. debug("%s: %s not enabled\n", __func__,
  481. _ep ? ep->ep.name : NULL);
  482. return -EINVAL;
  483. }
  484. spin_lock_irqsave(&ep->dev->lock, flags);
  485. /* Nuke all pending requests */
  486. nuke(ep, -ESHUTDOWN);
  487. ep->desc = 0;
  488. ep->stopped = 1;
  489. spin_unlock_irqrestore(&ep->dev->lock, flags);
  490. debug("%s: disabled %s\n", __func__, _ep->name);
  491. return 0;
  492. }
  493. static struct usb_request *dwc2_alloc_request(struct usb_ep *ep,
  494. gfp_t gfp_flags)
  495. {
  496. struct dwc2_request *req;
  497. debug("%s: %s %p\n", __func__, ep->name, ep);
  498. req = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*req));
  499. if (!req)
  500. return 0;
  501. memset(req, 0, sizeof *req);
  502. INIT_LIST_HEAD(&req->queue);
  503. return &req->req;
  504. }
  505. static void dwc2_free_request(struct usb_ep *ep, struct usb_request *_req)
  506. {
  507. struct dwc2_request *req;
  508. debug("%s: %p\n", __func__, ep);
  509. req = container_of(_req, struct dwc2_request, req);
  510. WARN_ON(!list_empty(&req->queue));
  511. kfree(req);
  512. }
  513. /* dequeue JUST ONE request */
  514. static int dwc2_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  515. {
  516. struct dwc2_ep *ep;
  517. struct dwc2_request *req;
  518. unsigned long flags = 0;
  519. debug("%s: %p\n", __func__, _ep);
  520. ep = container_of(_ep, struct dwc2_ep, ep);
  521. if (!_ep || ep->ep.name == ep0name)
  522. return -EINVAL;
  523. spin_lock_irqsave(&ep->dev->lock, flags);
  524. /* make sure it's actually queued on this endpoint */
  525. list_for_each_entry(req, &ep->queue, queue) {
  526. if (&req->req == _req)
  527. break;
  528. }
  529. if (&req->req != _req) {
  530. spin_unlock_irqrestore(&ep->dev->lock, flags);
  531. return -EINVAL;
  532. }
  533. done(ep, req, -ECONNRESET);
  534. spin_unlock_irqrestore(&ep->dev->lock, flags);
  535. return 0;
  536. }
  537. /*
  538. * Return bytes in EP FIFO
  539. */
  540. static int dwc2_fifo_status(struct usb_ep *_ep)
  541. {
  542. int count = 0;
  543. struct dwc2_ep *ep;
  544. ep = container_of(_ep, struct dwc2_ep, ep);
  545. if (!_ep) {
  546. debug("%s: bad ep\n", __func__);
  547. return -ENODEV;
  548. }
  549. debug("%s: %d\n", __func__, ep_index(ep));
  550. /* LPD can't report unclaimed bytes from IN fifos */
  551. if (ep_is_in(ep))
  552. return -EOPNOTSUPP;
  553. return count;
  554. }
  555. /*
  556. * Flush EP FIFO
  557. */
  558. static void dwc2_fifo_flush(struct usb_ep *_ep)
  559. {
  560. struct dwc2_ep *ep;
  561. ep = container_of(_ep, struct dwc2_ep, ep);
  562. if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  563. debug("%s: bad ep\n", __func__);
  564. return;
  565. }
  566. debug("%s: %d\n", __func__, ep_index(ep));
  567. }
  568. static const struct usb_gadget_ops dwc2_udc_ops = {
  569. /* current versions must always be self-powered */
  570. };
  571. static struct dwc2_udc memory = {
  572. .usb_address = 0,
  573. .gadget = {
  574. .ops = &dwc2_udc_ops,
  575. .ep0 = &memory.ep[0].ep,
  576. .name = driver_name,
  577. },
  578. /* control endpoint */
  579. .ep[0] = {
  580. .ep = {
  581. .name = ep0name,
  582. .ops = &dwc2_ep_ops,
  583. .maxpacket = EP0_FIFO_SIZE,
  584. },
  585. .dev = &memory,
  586. .bEndpointAddress = 0,
  587. .bmAttributes = 0,
  588. .ep_type = ep_control,
  589. },
  590. /* first group of endpoints */
  591. .ep[1] = {
  592. .ep = {
  593. .name = "ep1in-bulk",
  594. .ops = &dwc2_ep_ops,
  595. .maxpacket = EP_FIFO_SIZE,
  596. },
  597. .dev = &memory,
  598. .bEndpointAddress = USB_DIR_IN | 1,
  599. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  600. .ep_type = ep_bulk_out,
  601. .fifo_num = 1,
  602. },
  603. .ep[2] = {
  604. .ep = {
  605. .name = "ep2out-bulk",
  606. .ops = &dwc2_ep_ops,
  607. .maxpacket = EP_FIFO_SIZE,
  608. },
  609. .dev = &memory,
  610. .bEndpointAddress = USB_DIR_OUT | 2,
  611. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  612. .ep_type = ep_bulk_in,
  613. .fifo_num = 2,
  614. },
  615. .ep[3] = {
  616. .ep = {
  617. .name = "ep3in-int",
  618. .ops = &dwc2_ep_ops,
  619. .maxpacket = EP_FIFO_SIZE,
  620. },
  621. .dev = &memory,
  622. .bEndpointAddress = USB_DIR_IN | 3,
  623. .bmAttributes = USB_ENDPOINT_XFER_INT,
  624. .ep_type = ep_interrupt,
  625. .fifo_num = 3,
  626. },
  627. };
  628. /*
  629. * probe - binds to the platform device
  630. */
  631. int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata)
  632. {
  633. struct dwc2_udc *dev = &memory;
  634. int retval = 0;
  635. debug("%s: %p\n", __func__, pdata);
  636. dev->pdata = pdata;
  637. reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
  638. /* regs_otg = (void *)pdata->regs_otg; */
  639. dev->gadget.is_dualspeed = 1; /* Hack only*/
  640. dev->gadget.is_otg = 0;
  641. dev->gadget.is_a_peripheral = 0;
  642. dev->gadget.b_hnp_enable = 0;
  643. dev->gadget.a_hnp_support = 0;
  644. dev->gadget.a_alt_hnp_support = 0;
  645. the_controller = dev;
  646. usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE,
  647. ROUND(sizeof(struct usb_ctrlrequest),
  648. CONFIG_SYS_CACHELINE_SIZE));
  649. if (!usb_ctrl) {
  650. error("No memory available for UDC!\n");
  651. return -ENOMEM;
  652. }
  653. usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl;
  654. udc_reinit(dev);
  655. return retval;
  656. }
  657. int usb_gadget_handle_interrupts(int index)
  658. {
  659. u32 intr_status = readl(&reg->gintsts);
  660. u32 gintmsk = readl(&reg->gintmsk);
  661. if (intr_status & gintmsk)
  662. return dwc2_udc_irq(1, (void *)the_controller);
  663. return 0;
  664. }